An illustration of the latest development towards the integration of ultra-thin silicon bare dies within a flexible film. ChipInFlex is a generic wafer-level process for manufacturing a flexible label that integrates silicon components. Working on a silicon carrier helps achieve a high resolution of integration. The process described is the first to offer flipchip silicon dies interconnection within a flexible film and collective thinning.
Photo courtesy of CEA-Leti
Chip Scale Review and SMTA are pleased to announce the program for the 16th annual International Wafer-Level Packaging Conference (IWLPC). The conference will be heldOctober 22-24, 2019 at the DoubleTree by Hilton Hotel in San Jose, California USA.
The technical sessions on Tuesday and Wednesday are organized into three tracks: Wafer-Level Packaging, 3D Packaging, and Advanced Manufacturing and Test.The Wafer-Level Packaging (WLP) track features sessions on materials, reliability, metrology, processing, and new technology, such as Fan-Out WLP.
The 3D Packaging track features sessions on design, test, characterization, wafer bonding, chip stacking, and processing for Fan-Out. The Advanced Manufacturing track features sessions on process materials, equipment, inspection, and more.
Registration for IWLPC is now available online. Discounted rates are available for conference registration made on or before September 27, 2019.White Paper: System-level, post-layout electrical analysis for high-density advanced packaging