May • June 2016; Volume 20, Number 3
A plasma etch module that provides high-rate, low non-uniformity Si via reveal etch is
important to one of the final and critical steps in the 3D wafer stacking process flow
(see cover article on p.45). Combining a high-throughput Si thinning process with high
selectivity to the oxide liners delivers the smooth wafer surface needed for the subsequent steps to complete the 3D process flow.
Photo courtesy of SPTS Technologies
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A*STAR’S IME LAUNCHES CHIP-ON-WAFER CONSORTIUM II AND COST- EFFECTIVE INTERPOSER CONSORTIUM TO ADVANCE CHIP PACKAGING SOLUTIONS FOR HIGH-VOLUME MANUFACTURING
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Taipei, Taiwan (Sep 7-9) - SEMICON Taiwan is the premier event in Taiwan for microelectronics manufacturing. Connect with the companies, people, products and information shaping the future of design and manufacturing for semiconductors, nanoelectronics, MEMS, Photovoltaics and related advanced electronics.
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