November- December 1998
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Measuring the Manufacturability and Reliability of Electronic Assemblies
Because of shorter product development cycles, manufacturers need new tools and methods to assess the manufacturability and reliability of new interconnect technologies.
-By Petri Savolainen and Tommi Reinikainen Nokia Group, Helsinki Finland
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| Figure 1. Size reduction of cellular telephones (single mode analog or digital phones) |
Ball Grid Arrays (BGA), chip-scale packages (CSP) and flipchip technologies are solutions which meet the requirements of small package dimensions, high input/output (I/O) count and improved electrical performance.
Common to all these technologies is that the interconnections can be arranged in an array format with I/Os located beneath the component. Typical ball pitches vary between 1.0 and 1.5 mm with BGAs; 0.5 to 1.0 mm with CSPs and 0.1 to 0.25 mm with flip chip.
In addition to being relatively new to most electronics manufacturers, area-array package use increases the complexity of the assembly process: pads are smaller and solder paste printing becomes very difficult. Additionally, the joints cannot be inspected visually because the component body obscures the view to the joints.
Joining Methods
In some cases, novel joining methods have been developed to offer a feasible process for fine-pitch components. One example is the anisotropic, electrically conductive adhesives (ACAs) that enable very fine pitches, low process temperatures and lead-free, fluxless joining methods at low cost1. These materials were first targeted for display applications (TAB to glass and chip-on-glass) but are now shifting towards flip chip on board.
For example, Casio's credit-card-sized FM radio uses a new technology ACA in film form to attach ICs directly to an organic board. Because the joining process is very different from conventional soldering, the user must design the product to meet the requirements of the assembly process to realize the greatest benefits.
In parallel with the new component technologies, higher density printed wiring boards have been introduced. These new boards exhibit considerably smaller vias with relatively tight design rules for track width and space between tracks (Table 1). It is largely the smaller design rules that allow the routing of new, fine-pitch components, such as CSPs and flip chips, on the board. The microvias are formed by laser drilling, plasma etching or by photoimageable dielectric materials on organic layers added to the surface of the core board, which is fabricated using conventional board manufacturing methods (Figure 2).
| Table 1. Typical design rules for conventional (through-hole) and microvia-printed wiring boards are shown. (All dimensions are in µm) | ||||
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DH | Laser | Photovia | Plasma |
| Linewidth | 125 | 75 | 100 | 100 |
| Space between lines | 125 | 75 | 100 | 100 |
| Via diameter | 300 | 75 | 75 | 75 |
| Via pad diameter | 600 | 200 | 275 | 300 |
| DH=Drilled Hole | ||||
Microvia Layers
Most board manufacturers supply one microvia layer on each side of the core in volume, but two or more layers have been demonstrated on a smaller scale. Currently, the bottleneck for more widespread use of these technologies is that volume manufacturers exist mainly in Japan and their production is consumed largely by their domestic market2.
To achieve a robust assembly process with high yield, as well as the required reliability levels through the product lifetime, the manufacturer must address several issues when employing new technologies and materials.
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| Figure 2. Comparison of microvia vs. conventional drilled via |
When using fine-pitch and ultra fine-pitch technologies, the most important issues in the assembly process are solder application, inspection, testing, and component placement. All the major placement equipment manufacturers are either developing or already offer machines that can handle components from BGA to flip chip. Even with conventional surface mount technology, the solder application (paste printing) produces over 60% of defects detected post-reflow3. Hence, the solder application, inspection and testing are of great importance in assuring a high yield assembly process.
It is possible to attach the fine pitch components without any solder paste, i.e., by using the solder balls of the component and/or solder plating on the board pads. Then only flux must be applied before reflow. Consequently, the amount of solder that is applied can be adjusted very accurately, and the risk of short circuits or open circuits is minimized.
Paste Application
Because the pad area is extremely small, some considerations must be taken into account for solder paste application. Stencil openings are small, and, the printing process, as well as paste quality, should be tightly controlled to guarantee consistent amounts of solder on each pad.
The most important step after optimized design for manufacturability is process development. There are techniques that can be used to find the most critical process
parameters in the solder paste application. These techniques should be used to make the process as robust as possible, so that small changes in the environment or operator procedures will not affect product quality in volume production.
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| Figure 3. ACA flip-chip bonding parameters |
A very useful and well-proven method for optimizing the process parameters is the Design of Experiments (DoE).3-5 Orthogonal designs can be used to study the effects of different factors without any effects from other factors.
Factorial design involves all possible combinations which allow all orthogonal factors to be tested simultaneously. This saves time and effort, compared to testing, where one factor at a time is changed. Furthermore, this enables the user to estimate the interactions between the factors, because the effect of a single factor is evaluated against all other possible combinations.
An example of experimental design is the ACA flipchip bonding process. The ACA consists of a polymer matrix and a metallic filler with the latter providing the electrical conductivity. The amount of filler is between 2.5% and 10% in volume.
Consequently, the adhesive is an insulator in the X-Y direction and the electrical contact is made between the particles and the pads in the Z-direction (perpendicular to the plane of the adhesive layer).
The ACA is applied to the substrate as a thin (25 to 50 µm) layer, either as a film or paste. The process involves application of the ACA, aligning of the IC and bonding.
| Table 2. Factors and levels for flip-chip bonding with ACA. | ||
| Factors | Levels low | High |
| Temperature (°C) | 160 | 200 |
| Force (kg) | 5 | 10 |
| Time (s) | 5 | 20 |
Bonding
The bonding is performed with a dedicated tool that applies pressure and heat to the adhesive. The critical factors are the temperature that the adhesive reaches (defines the curing degree of the adhesives), the force that squeezes the particles and pads in contact and the length of time when heat and the pressure are applied.
Inputs for the process (factors) are temperature, force and the cycle time (when the temperature and force are applied as shown in Figure 3). For each factor, two levels are selected, as shown in Table 2.
The objective is to find a combination of the levels that produce the the most consistent quality for the interconnection between the IC and PWB, i.e., the best settings to achieve optimal electrical performance and maximum reliability.
Table 3 shows the orthogonal matrix for the experiment, which consists of eight trials2 to assess all possible combinations of the input factors. The response that is used to define the process quality must be easily measurable such as the electrical resistance and pull force, as shown in this example. All other factors that might affect the process result must be kept as constant as possible. The combination of factors that produces the lowest resistance and the highest pull strength is the most desirable.
The designed experiment results in two answers that the user needs: What are the settings that provide a robust process? And what is the sensitivity of the factors relative to the response? Usually the low and high values are coded as follows: -1 represents the low setting and + 1 represents the high setting. If three levels are used, 0 represents the midpoint. The coded values are used in the regression equation that mathematically models the response of interest.
Doyle and Barrett6 suggest that Design for Reliability (DFR) using DoE and statistical process control (SPC) methods should be a part of the product design process from the beginning.
The use of these methods helps to achieve better built-in reliability for the product and decreases the need for testing and verification. DFR, as a standard practice, offers the potential payback of higher yield, reduced burn-in time and fall-out, reduced warranty and field repair expense and an enhanced product reliability reputation.
In addition to the process parameters, the DoE approach can be used to define the correct design parameters, such as the solder pad sizes, solder ball size and the board thickness that gives the maximum reliability for the product.
In many cases, it is feasible to use thermo-mechanical finite element analysis to define a few of the best alternatives and conduct physical testing only on those alternatives. The FEA and other modelling methods will be discussed in more detail later.
Inspection and post-assembly testing can be used for assembly process control. The area array pattern of solder joints hinders effective visual inspection of the assembled BGAs, CSPs and or flip chips, because the joints are located under the component.
| Table 3. Full-factorial test matrix for ACA flip-chip process evaluation | |||||
| Run # | Input factors | Response | |||
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T | Force | Time | Resistance | Pull strength |
| 1 | 160 | 5 | 5 | X1 | Y1 |
| 2 | 160 | 5 | 20 | X2 | Y2 |
| 3 | 160 | 10 | 5 | X3 | Y3 |
| 4 | 160 | 10 | 20 | X4 | Y4 |
| 5 | 200 | 5 | 5 | X5 | Y5 |
| 6 | 200 | 5 | 20 | X6 | Y6 |
| 7 | 200 | 10 | 5 | X7 | Y7 |
| 8 | 200 | 10 | 20 | X8 | Y8 |
X-ray and Acoustic Techniques
X-ray and acoustic techniques are the methods used to inspect the quality of the solder joints for area array assemblies.
With both technologies, the user must establish proper qualifications for good and defective solder joints. These qualifications may require continuous refinement of the inspection results to avoid excessive rework. Due to the small dimensions of the solder joints, relatively high resolution is required from the inspection equipment.
Testing can be performed using automatic in-circuit testers or manual or semi-manual benchtop testing equipment. If the testability is considered in the early phase of product development, the in-circuit test system can be used to detect process defects, such as solder bridges and open joints, misplaced components and damaged components.
The critical issues are whether the testing can be performed fast enough to be used in-line and how to cover all the test points needed, as well as how the test pads can be located on the board without losing the benefits acquired by using finepitch components.
In many cases, the test pad diameter may be 0.5 mm when, for example, with flip chips, the component pitch may be 0.1 mm. As a result, more test pads will consume more board space.
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| Figure 4. Correlation between solder joint fatigue life and inelastic strain energy is illustrated. SPS model validation data and calculations for a ceramic CSP11 15 |
In area array packaging, the increasing number of interconnects and the decreasing volume of the interconnects creates new requirements for interconnect reliability assessment, compared to conventional surface-mount technology.
These demands, together with the increasing variety of different package types and new packaging materials, increase the amount of work needed for assembly and interconnect reliability assessments. Due to shortened product design cycles, a greater amount of work must now be completed in much less time.
Conventionally, physical testing has been the only method to estimate the reliability of the assembly in its operating environment. Testing has been based on various standards, which basically are such that the assembly can be assumed reliable if it lasts a certain number of hours or cycles in a particular test environment. Acceleration factors have been used to relate the performance in test to the performance in use environments, but this has led only to very approximate results because of the uncertainties in the value of the acceleration factor. Additionally, the true use environment is often not known.
Testing based on standards may lead to overengineering of some products, whereas others are qualified with requirements which are too low for their use environment and expected lifetime. Neither of these options is acceptable in today's competitive markets where both cost and reliability are important.
Reliability Modelling
It is obvious that new methods and tools are needed for assisting in reliability assessment. First, it is important to know the root cause of the different possible failure types and to understand the respective failure mechanisms.8
Second, it is important to know the true use environment of the product. This latter condition may be more complicated than it seems, because in the growing market of portable electronics different products are used in very different environments.
Knowledge of both the different possible failure mechanisms and of the product-use environment can be employed for selecting and optimizing the various tests needed for reliability assessment of the component assembly. Solder joint fatigue failure, which occurs because of the difference in the coefficient of thermal expansion of the different assembly materials, is the main life-limiting failure mechanism affecting surface-mount components interconnects.
In the scientific literature, much effort has been placed on analyzing solder joint fatigue and much of the work has been done with modeling.9 Modeling provides direct results in terms of stress distributions, lifetime, etc. In addition, modeling indirectly helps its users to understand the various issues which may affect reliability, since all the issues must be considered when building a numerical model of a physical structure.
Modeling can be done on many levels of complexity, accuracy and cost. The models used by packaging engineers for analyzing mechanical and thermo-mechanical loads on solder interconnects can be grouped into the three categories shown in Table 4.
In general, in the low order models, strain in the solder joint is used as the correlating parameter for joint-life calculations. The models can be used for first order approximations on the effect of thermal stresses in the joints, but their drawbacks are that they are not able to account for the complex interaction between fatigue and creep. They also do not take into account the effect of local CTE mismatch between the component (lead) and the joint or the substrate and the joint.
Today the most popular intermediate and high order models use accumulated strain energy as the correlating parameter to estimate the solder joint life.
Figure 4 shows the correlation between calculated strain energy and measured joint fatigue life a/A, where a is the characteristic number of cycles to 63.2% failures and A is the minimum load bearing area in the joint. The strain energy density (AW) in the figure is calculated with the SRS software but the slope is consistent with other strain-energybased models for SMT assembly reliability. This SRS model has been validated _ with several different components including 116 and 220 I/O ceramic CSPs.
The intermediate order models calculate the strain energy in one thermal cycle within a few minutes whereas the high order models (FEM) take from approximately one hour to one day to provide the solution.
In addition to the longer computing times, another drawback of high order models is that the use of general purpose FEA software requires much more expertise in model generation and post-processing than the intermediate order models which have integrated pre- and post-processors especially tailored for modeling electronic assemblies.
However, the advantage of the high order models over the intermediate order models is that they allow for modelling the assembly in much greater detail for loads, geometry and material properties.
Figure 5 shows a FE model of a 256 I/O TBGA on FR4 that is used for thermal stress analysis during temperature cycling and figure 2b shows the stress distribution in the solder joints of a BGA during temperature cycling. Due to the symmetry, only one quarter of the whole structure needs to be modeled. By using a parametric model, such as the one shown in the figure, the effect of a different geometry and material parameters can effectively be analyzed.
A parametric FE model is generated by an ASCII input file, and a change in the assembly geometry (e.g. die size, joint height) requires only that the user change the respective parameter in the input file.
Estimating FailuresWith FEA at present the number of cycles to failure can be estimated with the accuracy ±2X.14 But if some test results are available for a particular assembly, the modelling results will be much more accurate, since relative predictions are easier to make than absolute predictions.
For example, if test results are available for a certain temperature cycle profile, then FEA can be used to predict the interconnect life for another cycle profile with a better accuracy than ±2X. This type of analysis is especially useful when relating the test performance of an assembly to operating life conditions.
Unfortunately, a major bottleneck to conducting any modelling is the lack of reliable material data. Even the most sophisticated models are of no use if the material input data is wrong or inaccurate. Gathering the necessary material data may take a major part of the whole modelling work, and it is especially difficult if the exact compositions of the various assembly materials are not known.
Mechanical PropertiesSmall changes in the composition may affect the mechanical properties of some materials to such an extent that general handbook or data base16 values for the respective materials cannot be used. In that case, the options are to ask the component manufacturer to provide these values or to measure the parameters inhouse. Obviously, the former option would be more welcome to the reliability engineer.
For conducting state-of-the-art reliability assessment for electronics assemblies, the minimum requirements for the available material data are the elastic properties and CTE of each of the materials present in the assembly and the viscoplastic properties of the solder material.
Employing polymeric materials, the elastic properties and CTE change considerably at the Tg point, and some polymers may also exhibit visco-elastic or visco-plastic behavior.
Including the possible visco-plastic behavior of polymers in the various stress analysis models is not common today, but attempts for modelling this behavior do already exist.17
The majority of the thermal cycle modelling is done by assuming an homogenous temperature over the whole assembly. The stresses are assumed to result only because of the differences between the CTE of the various assembly materials. However, if the effect of operational heating is included in the model, the thermal properties (thermal conductivity, heat capacity) of the materials must also be available.
With an increasing number of different package types entering the market, modelling can reduce the time needed for testing when evaluating and qualifying these new packaging technologies. The package manufacturers should be able to provide the end user with the basic material data for their package materials, such as Young's modulus, Poisson's ratio and the CTE.
Measuring these values is not a cumbersome task and can be done with standard materials testing equipment. You can assume that the package manufacturer performs these measurements anyway during normal product development. These values should be easily available to the end user.
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| Figure 5. A parametric 1/4 finite element model of a 256 TBGA |
To survive and succeed in a competitive environment, such as the electronics industry, microelectronics manufacturers need ways to evaluate and qualify new component and printed wiring board technologies rapidly with reliable results.
Finite element modelling, accompanied by relevant reliability tests, can determine critical points in design which take into account the thermo-mechanical stresses arising in the product during testing and use. In addition, different materials and designs can be compared without extensive and expensive test runs.
References
- 1. "Microvia Substrates Ñ Investments and Opportunities" Prismark Partners, April 1998.
- 2. J. Kivilahti and R Savolainen, "Anisotropic Adhesives for Flip-Chip Bonding," Journ. of Electronics Manufacturing, No 4,1995.
- 3. L. Haslehurst and N. Ekere, "Parameter Interaction in Stencil Printing of Solder Paste," Journ. of Electronics Manufacturing, No 4,1996.
- 4. R J. Ross, Taguchi Techniquesfor Quality Engineering, McGraw-Hill, New York, 1996.
- 5. T. J. Green and R.G. Launsby, "Using DoE to reduce Costs and Improve the Quality of the Microelectronics Manufacturing Process," International Journ. of Microcircuits and Electronic Packaging, No.3, 1995.
- 6. R. Doyle and J. Barrett, "Design for Reliability: a Focus on Electronics Assembly," Soldering = Surface Mount Technology, No 3, 1997.
- 7. J.-R Clech, "Assessing the Solder Joint Reliability of Fine-Pitch SMT, BGA, Flip-Chip and CSP Assemblies," Tutorial at SMT/ESS/Hybrid'98, Nuremberg, Germany, 1998.
- 8. C. Pusarla et al., "A Physics-of-Failure Design Philosophy Applied to FlipChip Bonds," Microelectronics International, No.36, January 1995.
- 9. J. H. Lau and Y.H. Pao, Solder Joint Reliability of BGA, CSP, Flip-Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, 1997.
- 10. Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments, IPC-SM-785, November 1992.
- 11. J.-R Clech, "Flip-Chip/CSP Assembly Reliability and Solder Volume Effects," Surface Mount International '98, San Jose, Calif., August 1998.
- 12. S. Ling, A. Dasgupta, "Thermomechanical Stress Analysis of BGA Interconnects Using the MDRR Technique," Advances in Electronic Packaging, Vol.1,1997.
- 13. A. Dasgupta, C. Oyan, et al., "Solder Creep Fatigue Analysis by an Energy-Partitioning Approach," Trans. ASME J. El. Pack., Vol.114, June 1992.
- 14. R. Darveaux "Solder Joint Fatigue Life Model," TMS Annual Meeting, Orlando, Fla., February 1997.
- 15. R. Lanzone, "Ceramic CSP: Options for a Low Cost, High Density Technology," Advanced Packaging, September/October 1998.
- 16. EPMatLib 1.2, User's Guide, 1997.
- 17. Z. Qian, J. Yang and S. Liu, "Visco-Elastic-Plastic Properties and Constitutive Modelling of Underfills," Electronic Components and Technology Conference, Seattle, May 1998.
Mr. Reinikainen is a reaearch engineer at the Nokia Research Center. He received an M. Sc. in material engineeringfrom the Helsinki University of Technology. Contact him at rommi.reinikainen@research.nokia.com or +358.9.4376.6957.