Steve Berry and Sandra Winkler Contributing Editors

The debate regarding System-on-Chip (SoC) versus System-in-Package (SiP) continues to attract considerable attention.

Creating an SoC involves mixing different technologies onto a single piece of silicon, while SiP integrates the different technologies within a single packaged unit.

Required Functions in Close Proximity

The end result of either is that the required functions are in closer proximity than usual. Devices employing these formats can operate at higher speeds and consume less power than if the individual pieces were farther apart in separate packages. Moreover, less space is used on the PWB.

Any number of end applications can benefit from these dynamics. Certain medical devices-such as hearing aids and cameras that are swallowed to view the intestinal tract-require a small form factor. Any handheld, battery-operated device-such as a cellular telephone-can benefit.

SoC is created at the front end. The dies are large, complex and technologically challenging. Obtaining good yields can be difficult, and time-to-market may be slow due to a lengthy design cycle. If something goes wrong in the process, an entire wafer is affected, as opposed to a problem isolated to a single packaged part.

Placing multiple devices within a single package, on the other hand, allows for increased design flexibility and reduced overall design time in comparison to SoCs.

Space on the PWB can be saved with an SiP as the devices can be stacked vertically, such as is done in Tessera's new Pyxis package.

The Pyxis platform incorporates CSP technology with a stacked platform to create an RF module for cellular telephones and wireless electronic products in a LGA structure.

The module integrates Tessera's µBGA technology-gold-plated copper bond ribbon as an interconnection to polyimide tape. The copper ribbon provides for a faster conduit in relation to wire bonds, as it has a larger surface area to carry the electrons. Other elements in the module include inductors, capacitors, resistors and two GaAs die.

The first or lower layer is the polyimide tape; lead bonds and coil inductors are carved out of the one metal layer on the tape. Two GaAs die with flip-chip interconnection form the next layer; the flip-chip bumps face upwards to connect to an IPOC layer above.

The IPOC (integrated passives on chip) layer is an inexpensive layer of silicon that can incorporate resistors and capacitors in its structure. The bond ribbon leads connect to this IPOC layer.

AIT offers a SiP in a PLGA format. The ICs are mounted on specially designed die flags that employ a special PCB thermal via fabrication technology designed to draw heat from the die to the PWB.

Sanyo Electric Co., Ltd. has developed a SiP called the Integrated System in Board (ISB). A silicon chip in the package structure is attached to a copper-patterned film with conductive paste, and wire-bonded.

A Package Without a Substrate

The unique feature of this package is that it does not contain a substrate; rather, the copper film is the lower layer.

The result is a thinner package, one that can measure only 0.6mm thick if the die has been thinned to 0.33mm. Solder balls are ultimately placed on the backside of the copper film for attachment to the PWB. Heat dissipation occurs through the thin copper metals and the solder balls through to the PWB.

These are just three examples of the many SiPs that have been created in the last year. This is a technology that is rapidly maturing and offers a real alternative to SoC.