Steve Berry and Sandra Winkler Contributing Editors

Wafer-level packages (WLPs) are unique in that the die are packaged en mass while still in wafer form. Thus, the packages are truly die-sized once singulated.

Performance Benefits

WLP is low cost and offers the performance benefits of FCOB (flip-chip-on-board), but generally employs preformed solder balls on the underside of the package. WLPs, however may have solder bumps as well.

So, how are WLPs different from FCOB? The balls on a WLP often have a more standardized footprint and pitch versus the bumps on bare die flip chip. WLPs also generally incorporate some sort of environmental protection layer. Another feature that distinguishes a WLP from bumped bare die is that a WLP device is a fully tested part.

Although the markets for bumped bare die are growing rapidly, the uses of such die as FCOB are fairly limited. Generally, these bare die are placed within automobile parts and watches. FCOG (flip-chip-on-glass), however, is growing rapidly in the display-driver market.

But the potential for WLPs is far greater. Any IC with a favorable ratio of I/O count to die size is a potential wafer-level candidate.

Analog chips, including amplifiers, comparators, data converters, references and regulators-as well as application specific products-represent a huge opportunity for WLPs. For example, more than 20 billion analog ICs are produced each year.

Other areas for WLPs include CMOS logic devices, DRAMs, low-end microcontrollers and even PLDs. Discrete and passive devices also offer promising WLP markets.

Since WLPs are fully tested parts, they are also ideal for placement within stacked packages or SiPs, where multiple die are placed. These packages have the same issues as multichip modules, because the chance of failure for the entire packaged part is a multiplication of the failure rate of each device in the package.

Thus a device packaged as a WLP prior to placement within a multi-device package is the ultimate known good die.

However, there is some controversy regarding testing of WLPs. Since these packages do not have a standardized size, new test sockets must be built with each die shrink.

A better method is to test WLPs while still in wafer form. Testing in wafer form, however, is problematic. Getting registration across an entire wafer is complex, and doing so economically is even more troublesome.

Signal fidelity, dealing with noise issues, and testing so many I/Os at speed are other problem areas for wafer-level test.

Final Test at Wafer Probe

Moving to 300mm wafers will not make testing any easier at the wafer level. For some parts, final test may be performed as part of wafer probe. Once tested on the wafer, dicing the wafer into individual parts can damage the chips with nicks and cracks.

National Semiconductor has a solution to this issue with its Microfil package, which incorporates its Micro SMD wafer-level technology with wafer-level underfill applied prior to singulation. The underfill cushions or stabilizes the cut of the blade, and eliminates or minimizes the damage.

To accomplish this, the pre-applied underfill only partially covers the solder balls, so that during initial board placement the bumps make physical and electrical contact with the PCB. During reflow, the solder bumps shrink in height with normal collapsing, and the underfill material shrinks to a lesser degree and holds the device tight to the PWB, bonding the surfaces together. Post-curing is not required as the underfill is cured after one reflow pass.

With creative solutions to wafer-level packaging issues, such as wafer-level underfill, the outlook for WLPs appears extremely bright.