Infomation on products or services covered in this article

By Joseph Fjelstad, SiliconPipe Inc., San Jose [sipipe.com], and Craig Mitchell, Tessera Technologies Inc., San Jose [tessera.com]

The Tessera lead-bonded µBGA package is seen through the eyes of a comparator. (Photo by Pete Nuding)

In a real and substantive way, the invention of the integrated circuit (IC) in the late 1950s marked the birth of integrated circuit packaging.

Before the IC, discrete transistors were interconnected by means of a printed circuit and assembled into a module that performed the desired functions. Some early modules resembled and presaged later pin grid array packages.

These early devices were simple but robust interconnection structures onto which the transistors were mounted, interconnected and sealed (Figure 1). The equipment used to "package" them was also relatively simple and completely manual (Figure 2).

Fairchild and Texas Instruments, on the heels of their simultaneous development of the IC, each went in search of markets.

Fairchild's first IC products were called "Micrologic Elements," and were packaged in commonly available 8-lead TO-5 cans. TI, on the other hand, introduced both the IC and the new packaging format at the same time.

Figure 1. An early IBM Module (IBM)

The Dallas-based giant did so in striking fashion by distributing thousands of dummy packages in 1962-1963. This was a decidedly intelligent decision, because the dummy packages allowed potential users to become familiar with the new flatpack form factor, and helped users in their efforts to develop assembly techniques.¹

Enter the 'Flip Chip'

TI's IC packaging work employed nascent wire-bonding technology to make interconnections to the package leads. Mean-while, Robert McNutt, Edward Davis and Arthur Mones at IBM were developing and patenting² a technology for mounting silicon transistors onto substrates in the creation of hybrid circuits-the IC's parent technology.

The techniques developed at IBM would later become famously known as "flip chip." Independently, and a year or so earlier, Karl Siebertz of Siemens, Germany, patented a method for creating what could best be described as a near-chip-size beam-lead structure for transistors.³ A similar technique was independently developed at Bell Laboratories.

Figure 2. Devices were attached to their substrates with a machine like this in the early days. (ESEC)

These technologies yielded small devices and assemblies that, in many ways, resemble some of today's most advanced technologies. It was a truly auspicious time for the young technology, but marked only the beginning.

Ramping Production

While the first IC packages were largely designed for surface mount assembly, that technique did not lend itself well to volume production, and the devices were commonly hand-assembled.

Moreover, the early ICs and their packaging technologies were expensive, limiting potential applications.

For example, the TI Type 502 Flip-Flop, which was the first production IC TI offered to the commercial market, was announced in March 1960 sporting a hefty pricetag of $450.⁴ There was clearly a need to find new pathways and create viable economies of scale if the technology was to realize its potential.

Printed circuit technology with plated through-hole assembly capability offered just such an opportunity. Dual In-line Package (DIP) technology (credited to Rex Rice at Fairchild), stepped in to provide the standards for pinouts and footprints, first in ceramic and later in plastic. The DIP's standardized footprint also enabled the development of standard sockets for test and assembly, providing greater design freedom.

'Moore's Law'

While machines and methods were developed for the automated assembly of DIPs, the package format proved too space hungry and performance-limiting to keep pace with the increased I/O demands associated with ever increasing integration on the chip. At this point, the number of transistors was doubling every 18-24 months in accordance with "Moore's Law," an astute observation of Intel's Dr. Gordon Moore.⁵

SMT Redux

The combined effect of increased I/O, which caused the size and performance limits of the DIP to be reached, and the explosion in portable consumer electronics in the late 1970s to early 1980s, resulted in the emergence and ushering in of a host of new packages to replace the DIP.

These new devices displayed I/O terminals at the edges of the package like the DIP, but the leads were set at a finer pitch, not amenable to use of through-hole interconnection and assembly.

The packages were also thinner, often featuring I/O terminals located on all four sides to minimize the size of the package. This new package family was aptly dubbed "Quad Flat Package" or "QFP."

In addition, there were a host of other packages that were introduced at about the same time, such as the new SO or Small Outline package (originally called Swiss Outline when first invented at Phillips, circa 1968).

The family included SOTs (Small Outline Transistors), SOICs (Small Out-line Integrated Circuits) and TSOPs (Thin Small Outline Packages).

These devices are the direct ancestors of chip-scale packages and served nicely to reduce the size of many electronics assemblies. Moreover, they could be automatically assembled with good yields as long as the I/O pitch was not reduced to less than 0.5mm.

'Smaller, Faster, Lighter, Cheaper'

However, as I/O counts continued to rise, even these devices could not keep pace with the industry mantra of "smaller, faster, lighter, cheaper." It was clear that something new was needed.

While SO and TSOP packages gained widespread adoption for lower I/O, the pin grid array (PGA) was invented to meet the performance and I/O requirements of microprocessors in second and third generation PCs.

This format remains in use today for the Pentium 4, which now has 478 pins. In fact, led by Intel Corp., CPUs have driven the development of high pin-count IC packaging for some time now (Figure 3). The PGA was the first package to employ an area array, albeit with a partially depopulated interconnect. The reason for depopulating is typically to relieve routing congestion on the PWB and thereby simplify the PWB design and manufacturing process.

Figure 3. CPUs have driven the development of high pincount IC packaging. As shown, microprocessors have been packaged in nearly every format over time. (Intel Corp.)

PGA Reincarnated

The PGA inspired the development of the ball grid array (BGA). PGAs provided more I/O in less space than QFPs, even when the former's I/O pitch was coarser. Thus, in the late 1980s and early 1990s, BGAs arrived as the surface-mountable incarnation of the PGA.

BGAs took a while to catch hold as the industry grappled with quality assurance and reliability engineers' concerns regarding the myriad of blind interconnections that resided beneath the package.

Once comforted by learning, however, that reliable interconnections could be readily made with even higher yield than often realized with leadframe-based packages, the industry embraced the concept and BGA technology took off.

Around the same time, the electronics industry was trying to define and implement what many considered the "ultimate solution" for manufacturing electronics, the multichip module (MCM).

MCMs were not all that new; they had deep roots in the hybrid circuit industry, but the challenge was to make what was largely a military technology into a commercial one. Probably the most daunting of the challenges for MCMs was the availability of known good die (KGD).

Figure 4. The MicroSMT package in these cutaway views was among the first chip-scale packages fabricated completely on the wafer. (Source: ChipScale Inc.)

Innovation from Elmsford, N.Y.

Lack of KGD caused the industry to flounder, as the concern of compound yield and expense loomed large. While the industry sought ways to procure good die in unpackaged formats, innovators at a small company called Tessera in Elmsford, N.Y., saw an opportunity to provide packages that were near the size of the chip, to solve the cost problem.

The new package provided the benefits of flip chip in a protected, easily tested and assembled format.

The device they developed is known today as the µBGA package (MicroBGA). At about the same time in San Jose, another small company, M-pulse, (later ChipScale Inc.), was developing a method for packaging devices directly on the wafer in a product called the MicroSMT (Figure 4).

Getting Down to Chip Size

As is the case with most new technologies, there was a desire to define "CSP."

One reason was that the term was used for both chip-size package and chip-scale package. Chip size is self-defining; however, chip scale is a bit more nebulous. As a result, chip-scale packaging has taken on a number of definitions since the introduction of the technology.

The chip-scale package has been variously defined as: 1. a packaged IC with a footprint not greater than 1.2x the size of the die, 2. a packaged IC whose size is not greater than 1.5x the volume of the die, 3. a minimally packaged IC with a) I/O lead pitch of 1.0mm or less and having the package body extending no greater than 1.0mm beyond the each edge of the chip, or 4. simply "a minimally packaged IC."

Like the package formats that preceded them, early chip-scale packages took direction from what came before. Thus, CSP constructions employ the full complement of interconnection technologies used for earlier surface-mount packages.

Strain Relief

Rigid and flexible substrates and modified leadframes all serve the needs and purposes of CSP devices. One important lesson learned in CSPs was that, depending on the size of the chip, there is a need to provide strain relief in the package to decouple the chip from the substrate to which it is mounted.

Figure 5. Leadless leadframe packages such as the MLF, which is generically a QFN, have become increasingly popular for few-I/O applications. (Amkor Technology Inc.)

This is due to the difference in CTE of the silicon chip and the substrate to which it is mounted. The difference could be as much as a factor of 6. If not adequately addressed, the I/O interconnections on the package might fail prematurely, leading to total product failure.

In earlier-generation packages, mechanical compliance was provided by the long leads of the IC package. Lacking such leads on area array devices, Tessera's engineers developed a patented technology to decouple the stresses within the package. This technology is now widely used by IDMs and packaging foundries.

Today, chip-scale solutions continue to vary with the needs of the product. For very small die with few I/O, packaging engineers have determined that leadframe packages without leads can perform reliably for a range of applications.

For example, Amkor's Micro Lead Frame (MLF) package, a member of the quad flat pack-no lead (QFN)/small outline, no lead (SON) family, has proven quite popular (Figure 5). The QFN package format is seeing tremendous success, replacing many of the earlier SOIC and TSOP package applications.

In addition to the new package developments at assembly houses, large chip makers such as IBM, Intel, Motorola, National Semiconductor and TI conduct extensive research in packaging.

Figure 6. Intel's BBUL packaging is bumpless and does not employ solder bumps. (Intel Corp.)

Intel, for example, has developed BBUL (bumpless build-up layer) packaging for microprocessors (Figure 6). Being bumpless, it does not employ tiny solder bumps to attach the die to the package interconnects.

Layers are built-up around the silicon die, rather than being made separately and bonded to it. Intel says this technology makes for thinner and lighter packages and offers electrical performance and power advantages. With BBUL, multiple chips (CPUs, memories, etc.) can be interconnected inside the same package.

Wafer-Level Packaging

Beyond chip scale, the evolution of the semiconductor package followed its way to the next logical step, packaging at the wafer level, which offered a host of potential cost savings, and thereby attracted significant attention and spawned much research both in industry and in academia.

Wafer-level packaging had been explored earlier by ChipScale Inc. Other companies also redistributed I/O on the surface of semiconductor wafers, and IBM pioneered it with the well-known C4 (controlled collapse chip connection) process.

Casio, Flip Chip Inc., Fujitsu, Georgia Tech, Motorola, ShellCase Inc. and Tessera are just a few of the companies that either proposed or offered WLP processes.

One such concept suggested the use of the package to share functions with the IC and accommodate power, ground and cross-chip interconnections (Figure 7).

While WLP is attractive, there are sobering concerns of cost and yield to be considered. To be cost-effective, the package yield must be nearly identical to the wafer-chip yield.

Figure 7. This concept suggests the use of the package to share functions with the IC and accommodate power, ground and cross-chip interconnections. Wafer-level packaging potentially offers more than simple I/O redistribution. (Tessera Inc.)

Another concern involves die shrink. With each die shrink, the package footprint will likely change.

As a result, PWBs with wafer-level-packaged devices might well require a redesign with each die shrink-which is both time consuming and costly. Still, the WLP concept remains attractive, since it promises massively parallel processing and test.

Folding and Stacking CSPs

Though chip packaging was reduced to true chip size using WLP, that did not mark the end of the road for CSPs. Product developers eager to put more function into the same footprint hit upon the idea of stacking CSPs.

Again, the roots of this concept go back to the development of "memory bricks" for military products in the 1980s. Com-panies such as Irvine Sensors, DensePac, and Stacktek developed volumetric packaging solutions for memory chips. While effective, the structures were monolithic and required more than average skill to assemble.

Figure 8. Chip stacking within a package is a commonly used solution. One highly popular application is the integration of flash memory and SRAM in a single package

Since chip-scale packaging was widely embraced by the memory industry and by computer users hungry for ever increasing quantities of memory, the idea of stacking finished memory packages was also not long in arriving. Concurrently, there was been a surge in interest in stacking chips within a package. (Figure 8).

This approach, commonly referred to as chip stacking, is widely used by both semiconductor manufacturers and subcontract assemblers.

Although the die is typically flash memory and SRAM, more complex stacks with three, four and five or more die have been assembled and shipped in volume. The issues that tend to limit adoption of such of such chip stack solutions include compound yield, assembly complexity, sourcing KGD and managing multiple die vendors.

While some product developers are having some success with this challenge, others have responded to the concern with alternative stacking approaches, such as package stacking.

Figure 9. Stacked packaging technologies, such as the µZ Fold-Over and µZ-Ball Stack offer greater functionality in less space than conventional packages. (Tessera)

By enabling more functions in a single footprint, package stacking technologies, such as Tessera's µZ Fold-Over and µZ-Ball Stack (Figure 9), have rapidly gained acceptance in electronic product design.

Stacking concepts for same function technologies, such as DRAM, can also be performed in traditional packages such as TSOPs, but newer and smaller packaging concepts have been developed to fill this important need for leveraging the Z axis.

Looking Ahead

With all that has transpired since the development of the integrated circuit and the first IC packages, the evolution of IC packaging is far from over.

New concepts and technologies continue to come to the forefront offering themselves as potential solutions to the ever-expanding world of electronics. One realm that offers significant promise is in chip-to-chip interconnection.⁶

In spite of the excellent performance of copper as an interconnection medium, this material is often assumed to be too slow for next-generation electronics applications requiring GHz speeds.

In truth, copper can transmit signals at near the speed of light if properly configured. The challenge is not so much achieving signal speed as avoiding signal degradation. Signal integrity experts have been pointing out for the last few years all of the issues and hurdles associated with present printed circuit materials, manufacturing practices and design approaches.

With the understanding that the fundamental objective is to get the signal to its objective cleanly and clearly and as fast as possible, SiliconPipe Inc., San Jose, conceived of a new family of novel IC packages and technology where all high-speed signals are launched from the surface of the chip package with I/O drivers connected directly to those signal lines though a controlled impedance cable to the surface of another chip package of similar construction (Figure 10).

Figure 10. The speed bottleneck can be broken by moving high-speed signals to the top surface of IC packages and interconnecting them by means of controlled impedance flexible circuit cables. (SiliconPipe)

This technology allows signals to be transmitted directly between chips with virtually no performance-sapping interruptions. Simplicity is one of the important overarching results of this approach.

The method allows for a reduction in layer count in both the IC package and the substrate to which it is mounted. These proprietary copper-based interconnection solutions for high-speed electronic applications will be made broadly available in the near future.

Summing Up

IC packaging technology continues to grow in importance, if not in size. In many cases, the IC package is as important as the silicon it contains. In fact, the package is now the keeper of the performance gate and is no longer considered an "unfortunate necessity."

References

1. National Museum of American History's Chip Collection Website-The Texas Instruments Collection http://smithsonianchips.si.edu/index2.htm

2. U.S. Patent No. 3,292,240

3. U.S. Patent No. 3,184,831

4. http://smithsonianchips.si.edu/index2.htm

5. Intel.com

6. J. Fjelstad, "Electronic Super Highways for Chip-to-Chip Communication," Circuitree, January 2004.

Mr. Fjelstad, co-founder of SiliconPipe, Inc., has 32 years of international experience in electronic interconnection and packaging. Six of those years were with Tessera, where he was its first appointed Fellow. Mr. Fjelstad has authored or co-authored several books on IC packaging and has more than 120 U.S. patents either issued or pending. [j_fjelstad@sipipe.com] Mr. Mitchell is Tessera's vice president of marketing. During his decade at the company, he's served in a variety of engineering and management posts, including vice president and director of memory business. He received a BSEE from Manhattan College, New York. [csmitchell@tessera.com]