Terrence E. Thompson Senior Editor

Facing strong competitive pricing and-in some areas-performance pressures, Universal Instru-ments is quickly becoming leaner and more responsive. With three-shift manufacturing, the 37,161 square meter Conklin South facility in Binghamton, N.Y., turns machine orders into finished tools in days.

I recently returned from Universal headquarters following a multi-day press tour for trade journalists provided by the company. In case you didn't know, Universal is a very large link in the Dover chain that also includes DEK, Everett Charles and OK International.

Packaging Hierarchy Blurring

Ian P. McEvoy, UIC president, said, "We see a growing collapse of the traditional packaging hierarchy into one level of assembly. Distinctions between PWB surface mount assembly, with much smaller boards and tight pitches, system-in-package or other packages, are blurring."

Universal's Jacques Coderre, advanced semiconductor assembly product manager, addressed this convergence for the press. He showed some in-production SiP assemblies including Bluetooth, laser diode modules, FCIPs, VCSELs and flip-chip-on-flex for disk drives.

SiPs with Chips

Despite ongoing hype about system-on-chip, the fact is discrete component volumes always exceed IC shipments, and many discretes end up in SiPs with chips. Other components end up in module packages, too, including optoelectronic and MEMS devices, Coderre observed.

McEvoy also noted, "We're looking at major packaging opportunities in China, as well as the rest of Asia. That's where most high-volume, low-cost products are being made."

In February, the company opened a $5 million, 4,700m2 manufacturing facility in Shekou, Guangdong Province. It serves as a base for their Asian business and provides hands-on process and manufacturing training support for existing and potential customers in China.

"The new facility includes research, engineering and product assembly," said McEvoy.

Still, Universal Instruments is counting on viable low-to-moderate volume assembly in the Americas and Europe [uic.com].

Intel's "tri-gate" transistor design

Triple-Gate Transistors

Intel Corp. revealed details on its advanced "tri-gate" transistor design at the 2003 Symposia of VLSI Technology and Circuits in Kyoto, Japan, recently.

The microprocessor giant will now move from research to the development phase. Since originally described last year, researchers have shrunk the size of the transistor's gate length from 60 to 30nm. Smaller gates switch on and off faster, enabling faster µPs.

Scalability, performance and manufacturability suggest the start of initial production by 2007 with 45nm processes, according to Sunlin Chou, senior vice president/GM at Intel's Technology and Manufacturing Group.

Promising Nanotechnology

"The results place non-planar, 3-D transistor structures among the promising nanotechnology innovations that we will use to extend silicon scaling and Moore's Law well into the future," he added.

The 3-D gate structure, a raised plateau with vertical sides, simultaneously allows electrical signals to use the top of the transistor gate and both vertical sidewalls. This effectively triples the space available for electrical signals to travel.

The transistor can be manufactured in high volumes and addresses the growing CMOS current leakage problem. The tri-gate leakage is far less than a planar transistor of the same size. Devices have been successfully manufactured at Intel's 300-mm wafer fabrication facility (Fab D1C) in Hillsboro, Ore. [intel.com]