The International Magazine for Device and Wafer-Level Test, Assembly, and Packaging Addressing High-density Interconnection of Microelectronic IC's including 3D packages, MEMS, MOEMS, RF/Wireless, Optoelectronic and Other Wafer-fabricated Devices for the 21st Century

Feature Article
Evaluating Wafer-Level Solder Reflow Options to Maximize Yield

By Thomas Goodman and Peter Elenius, E&G Technology Partners, Tempe, Arizona, and John Marcin and Carson Richert, Radiant Technology Corp., Fullerton, Calif.

Most surface mount or general purpose soldering processes do not meet stringent wafer-level bump reflow requirements. This article compares the results of an IR-based conduction wafer-reflow-specific process to more general-purpose alternatives.

There are a variety of systems that can be employed to reflow wafer solder bumps. In many instances, however, existing systems fail to address the critical process parameters required for wafers.

The basic bump formation and reflow processes are:

  • Solder paste bump formation where paste is either deposited through a stencil(1) or deposited into an in-situ dry film mask(2). Solder paste technologies can readily accommodate many solder alloy compositions.

  • Solder bump reshape is the subsequent reflow for evaporated, plated and other bumping technologies to make a spherical bump from as-deposited material or to remove probed bump damage. Reshaping usually occurs with a hydrogen atmosphere or flux to reduce solder oxides.

  • Discrete solderball attach is a preferred technique for forming WLP solder balls. Balls of 250- to 500-micron diameter are placed on UBMs coated with flux, then reflowed. A FC option uses 80- to 250-micron diameter solder balls to deposit solder bumps for lower bump count FC wafers(3).

Oven Technologies

The primary oven types used today for reflowing solder on wafers are conduction, forced convection, infrared and muffle. Some reflow furnaces combine more than one of these technologies.

Conduction technology uses the transfer of heat from a hot plate to the bottom of the wafer. Conduction heating is robust for solder bump reflow, particularly for solder paste bumping. By heating a wafer from below, the silicon conducts heat to the UBM, which heats and activates the flux to create a reliable solder joint. The drawback of some conduction systems is the "hot plate" concept that can result in non-uniform heating and mechanical stress on the wafer.

A second reflow oven type, forced convection technology, is used in surface mount and other reflow processes. Heated process gas (typically nitrogen) is forced at high velocity onto the wafer with solder to be reflowed. Heat is transferred by convection to the wafer and solder. Because the system heats from the top down, drying of the flux may result.

Reflow Process Requirements and Corresponding Furnace Design Elements
Reflow Requirement Reflow Oven Design Element
Rapid thermal response for low cost of ownership (CoO) IR lamp heat source
Conductive heating to facilitate oxide reduction at the solder/UBM interface Continuous conduction belt heating
Non-turbulent flow to minimize ball/paste/flux displacement and/or flux drying Laminar flow gas through porous walls
Flexibility in heating and cooling Multi-belt transport
Interface to high volume production lines Automation

The third technique, infrared heating, employs lamps that emit medium and short wavelength radiation. This radiation interacts with wafer and solder, causing both to heat. With a high degree of short wavelength IR, profiling can be difficult, as a change in a material's emissivity will change the rate at which it absorbs heat.

Finally, muffle technology employs a process chamber and belt surrounded by a heated metal shell (i.e., the muffle) for the entire belt length. Heat transfer occurs through a combination of medium wavelength IR radiation from the muffle and convection.

Ambient temperature process gases such as nitrogen and/or hydrogen are introduced via a sparger tube, normally located over the wafers. The insulation and muffle have significant thermal mass, limiting quick response to varying loads and profiles. The inability to shut down the furnace if it is operated less than 24 hours per day, however, can result in a high cost of ownership.

Figure 1. Basic construction of a solder bump

Combing IR and Conduction Heating

One method that addresses the exacting needs at the wafer level and utilizes the best attributes of two processes is a reflow oven system that combines IR and conduction heating technologies. This system employs infrared lamps to heat a belt below the wafer; the belt then transfers heat into the wafer backside, which conducts heat to the under-bump metallization (UBM) for flux activation and solder reflow.

Heating in this manner can minimize voids in high-volume production flip-chip bumping. By heating the UBM first, the flux is activated, which effectively prepares the UBM surface for better wetting and reflow. All wafer-level solder structures share a basic arrangement where solder is reflowed to the UBM on the final metal pad, as shown in Figure 1. The process of reflowing the solder on the wafer has been considered to be of secondary importance in the solder bump formation process and has not received significant attention. Equipment and methods developed for substrate- or board-level processes are often put into use with little regard for their effect on the final solder bump.

Important bump issues that impact yield, such as voiding, wetting, and intermetallic formation, all depend on reflow control. The primary technologies for depositing solder on UBM for FC applications are solder paste deposition or plating. For WLP, where larger solder volumes are required, discrete solder balls are placed. Each has unique reflow challenges.

Critical Reflow Requirements

Each solder bumping process has unique reflow requirements:

  • Low oxygen levels minimize oxide formations on solder paste particles and UBM surfaces and minimize the charring of solder paste flux and carrier. For hydrogen reflow, an O2 level of less than 10 ppm prevents solder oxides. This is important for all types of wafer-level solder reflow (solder paste, solder reshape, and solder sphere).

  • Repeatable temperature profiles ensure consistent flux activation for oxide reduction and intermetallic formation.

  • Continuous temperature profiles assure high yields for varying wafer types, sizes and ball counts, especially solder sphere reflow. A continuous temperature (e.g., without temperature steps) can prevent flux volatiles from boiling. This, in turn, may prevent solder balls from moving and bridging together.

  • Compatibility with an in-situ dry film requires temperature and atmosphere control to prevent unwanted changes in the film's physical properties.

  • Flux volatile escape allows volatiles to be removed by the surrounding atmosphere.

  • A flux management system will avoid tainting the furnace with flux residues that could affect furnace performance or become a wafer contaminant.

No movement of solder from process gas or wafer jarring prevents missing balls or solder bridging. The close proximity of solder balls may allow bridging as strong gas flows can move solder balls.

Figure 2. IR-based conduction heating

Rethinking Reflow

A reliable solder WLP interconnection demands precise thermal processing. Several key oven attributes are also needed to maximize yield.

The use of infrared-based conduction involves heating a high-density mesh Nichrome conveyor belt which heats the wafer from below. IR lamps allow rapid thermal response, important for profile change or on-demand heating. The mesh belt absorbs between 95 to 98 percent of the incident IR radiation. IR conduction heating is shown in Figure 2.

In this process, IR is absorbed by, and heats, the high-density mesh belt. Heat is conducted to the wafer's final metal and UBM below the solder. The UBM heats the flux for activation before solder reflow, which promotes effective oxide reduction and good intermetallic formation. Solder reflows from the bottom up.

Flux Drying Is Eliminated

The absence of active heating above the solder eliminates flux drying or "skinning," which can trap volatiles or other materials that promote void formation. The mesh belt, meanwhile, conducts heat into the wafer with a smooth profile, unlike hot-plate type conduction ovens with their distinct heated zone steps.

Figure 3. Cross-sectional Diagram of Laminar Flow System

The oven's low-velocity laminar gas flow enables the process gas to provide a virtually oxygen-free environment. In the system, shown in Figure 3, gas is fed into the process chamber through porous ceramic walls, flowing gas slowly and smoothly into the process chamber. Low velocity gas provides an inert gas blanket but does not disturb solder spheres that may be shifted by higher velocity flows.

One method that addresses the exacting needs at the wafer level and utilizes the best attributes of two processes is a reflow oven system that combines conduction with IR technology.

Additionally, low-velocity gas does not dry the solder paste flux or flux used for ball attachment. Preheated gas allows precise control of temperatures whereas cool gas could cause temperature gradients. This laminar gas flow system consistently provides oxygen levels <10 ppm.

Gas is swept out of the chamber and exhausted, removing volatiles and other reflow by-products. This ensures a clean process by removing gaseous components that may condense on the wafer or oven walls, causing contamination. The oven also employs a multi-belt system with separate belts for loading, heating and cooling zone process flexibility and precise temperature control, shown in Figure 4.

Figure 4. Multi-belt wafer transport system

Because the hot belt does not need to be cooled, quick thermal response and high thermal efficiency are achievable. Rapid, controlled heating is possible; wafer transfer from hot belt to cold belt allows rapid, controlled cooling and fast profile changeovers. While this is not a requirement for high volume wafer bumpers running one process, factories using one oven for reflowing of multiple products or solder alloys could use this flexibility.

Figure 5. Correlation between FEM and experimental data for oven profile

Modeling Results

The authors performed a finite element analysis to model the profile of the new system. A 9 x 9 element array of silicon was modeled using the sum of heat-in and heat-out to account for the effects of conductive heating from the belt and from the nearest neighbor elements, radiative heating from surrounding walls, and convective heating from process gas. As expected, the contributions from radiative and convective heat sources were quite small compared with those from conductive heating.

The model determined that the temperature difference between the mesh belt and silicon wafer is typically less than 5°C, indicating good conduction. A comparison of modeled results with experimental measurement (Figure 5) shows good correlation between the two. IR-based conduction ovens used in high-volume 300mm wafer bumping fabs have shown that this heating mechanism produces bumps with few voids.


Several wafer-level solder reflow technologies are in use yet most were not designed for FC or WLP reflow. Ovens based on analyses of process requirements for wafer-level solder reflow work well. Modeling and measured results show IR-based conductive heating provides precise temperature control within the belt and the wafer.


1. S. F. Popelar and C.A. Erickson, "A Low Cost Wafer Bumping Process for Flip Chip Appli-cations", 5th Annual Emerging Technologies Symposium Proceedings, Chandler, Ariz., November 1998, pp. 536-540.

2. T. Hamano and A. Papalexis, "Wafer Bumping Solutions: Consumer to Advanced Applications," Advanced Packaging Magazine, October 2002, pp. 21-24.

3. E. Hashino and K. Shimokawa, Y. Yamamoto and K. Tatsumi, "Micro-Ball Wafer Bumping for Flip Chip Interconnection," Proceedings of the IEEE 51st Electronic Components and Technology Conference (ECTC),Orlando, Fla., May/June 2001, pp. 957-964.

Mr. Goodman is cofounder and managing partner of E&G Technology Partners. He most recently was manager of strategic business development at Kulicke & Soffa's Flip Chip Division (formerly Flip Chip Technologies).He earned a master's degree in macromolecular science and engineering from Case Western Reserve University and a bachelors' degree in polymer science from Penn State University. []
Mr. Elenius is also co-founder and managing partner at E&G Technology Partners. Most recently, he was vice president of technology and chief technical officer at K&S's Flip Chip Division. He holds a master's degree in manufacturing systems and a bachelor's degree in mechanical engineering from the University of Wisconsin, Madison. []
Mr. Marcin is vice president of marketing at Radiant Technol-ogy Corp. His extensive industry experience includes posts at Conexant, Texas Instruments and Hughes Microelectronics. He earned a master's degree from the University of Southern California and a bachelor's degree in material science and engineering from the University of California, Los Angeles. []
Mr. Richert is a co-founder and executive vice president of Radiant Technology Corp. He has extensive experience in thermal processes for semiconductor packaging and advanced materials. Richert pioneered the use of IR radiation for surface mount reflow, FC attach and wafer bump conduction. []
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