Chip Scale Review Magazine

August - September 2008

Chip Scale Review is produced for a worldwide audience of engineers, specialists, researchers and end-users of chip-scale electronics, with a circulation of 24,000 worldwide. Chip Scale Review covers the chip-scale, flip-chip and wafer-level packaging market with a thoroughness unmatched by any other magazine.

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STATS ChipPAC’s Manufacturing Agreement With Infineon on First Generation Wafer-Level Ball Grid Array eWLB Technology

Singapore—STATS ChipPAC Ltd., a semiconductor test and advanced packaging service provider, announced it has entered into an agreement with Infineon Technologies AG to provide manufacturing services for products based on Infineon’s first generation embedded Wafer-Level Ball Grid Array (eWLB) technology. [more]

EMC3D Consortium Develops Process And Cost Model For Interconnect Thru-Silicon-Via (iTSVTM) Structures

Santa Clara, Calif.—A cost model for interconnect TSV using many of the same process steps of the current packaging TSV have been created by the TSV consortium EMC3D. [more]

IMEC and CEA-LETI Gear Up Cost-Effective Silicon Photonics Prototyping Service

Leuven, Belgium and Grenoble, France—IMEC [imec.be] and CEA-LETI [leti.cea.fr] launched ePIXfab, the continuation of their successful multi-project wafer silicon photonics prototyping service started in 2006. Co-funded by the European Union through the Seventh Framework Program and coordinated by IMEC, ePIXfab aims at reducing the large barriers for access to and market take-up of silicon photonics technology by focusing on reduced cost, risk and design effort, education, and roadmapping. [more]

Dow Corning Demos Manufacturing Process and Materials To Significantly Increase Solar Panel Production Rates, Decrease Cost of Solar Power

Midland, Mich.—Dow Corning Corp. has demonstrated a manufacturing process featuring new developmental silicone materials that significantly increases the production rate of solar panels, effectively lowering the cost per watt of solar power. [more]

Lord Corporation Develops 5W & 6W High-Conductivity Thermal Greases for High-End Chips

Cary, N.C.—LORD Corporation, a supplier of thermal management materials, adhesives, coatings and encapsulants to the electronics industry, has developed high thermal conductivity greases designed to maximize the heat transfer from high-end chips to the heat spreader. [more]

Die Products Consortium’s KGD Packaging & Test Workshop, September 7-10, 2008

Napa, Calif.—Hosted annually by the Die Products Consortium, the KGD Workshop focuses on semiconductor die products test, assembly, manufacturing, and business issues at the forefront of the microelectronics industry. The 2008 KGD Packaging & Test Workshop will be held September 7-10, 2008 at the Embassy Suites in Napa Valley. [more]

5th Annual International Wafer-Level Packaging Conference Will Have Its Largest Program in History, October 13-16, 2008

San Jose, Calif.—This year’s fifth annual International Wafer-Level Packaging Conference (IWLPC), October 13-16, will be the largest ever, according to Dr. Ken Gilleo, IWLPC general chair. [more]

SEMATECH to Host TSV 3D IC (Vertical Interconnect) Workshop on Manufacturing and Reliability Sept. 25-26, in San Diego

San Diego, Calif.—SEMATECH will host global experts representing a broad spectrum of the semiconductor industry at a workshop designed to explore manufacturing and reliability challenges for three-dimensional integrated circuit (3D IC) products. The forum, entitled “Manufacturing and Reliability Challenges for 3D ICs using TSVs,” will be held at the Del Mar Fairgrounds in San Diego, California. [more]