An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics January - February 2000 Email the editor

System-in-a-Package Applications Should Grow Rapidly this Decade

As the new decade unfolds, one exciting trend in the semiconductor industry is a broadening of focus from what has been, perhaps, an overemphasis on system-on-a-chip IC solutions, to a vision that includes a multi-chip-plus-passives system-in-a-package (SiP) design.

SoC and SiP provide alternate-and sometimes complementary-paths to the same goal of economically satisfying the system application requirements through a combination of IC chip design and packaging. Which is the better Þt for a speciÞc application depends on market size, company resources and performance trade-offs.

SiP shows promise where time-to-market or NRE costs are especially critical, where multiple wafer fab process technologies are required to achieve certain combinations of digital and analog performance or simply where it makes sense not to carry integration levels all the way to a single-chip system.

In considering SiP for high-speed digital and RF designs, it is important to recognize the advantages of adding passives inside the package, immediately adjacent to the silicon, to minimize the effect of parasitics. The laminate or ceramic substrate in area-array packages is effectively a Þne-pitch circuit board, and SiP assembly equipment can economically assemble both chips and passives into the same package. IC packages are converging on the SiP from a number of directions. Ceramic multi-chip modules (MCM) have been available for many years, of course, but SiP is destined for high-volume, low- cost applications.

There have been early indicators of the SiP trend. Consider that, even at Intel, with its sophisticated semiconductor process capabilities, various Pentium generations have used the SiP approach to combine processor and cache whenever the required cache size was inappropriate for the process technology generation.

Since early last year, one of the hottest cellular telephone packaging technologies has been the stacked chip-scale packaging that places SRAM and flash in the same tiny, economical surface-mount package. This 3D packaging approach will soon be used for combining logic and memory in addition to different types of memory.

Much, but not all, of the resources required to make SiP mainstream are already in place.

There are also areas where more work is required before the SiP can become a mainstream design approach. For example, chip makers and test system vendors must cooperate further on techniques for wafer-level testing so that chip makers can supply quantities of known-good die at a reasonable cost. Also, the number of suppliers of interposer substrate material needs to increase.

Led by portable wireless devices, the application of SiPs should grow rapidly in this decade. These devices generally combine requirements for small size and high integration with the need to combine various semiconductor process technologies (such as CMOS, bipolar silicon and gallium arsenide) with passive components-John Boruch, President, Amkor Technology Inc.

Amkor is the world's largest provider of contract semiconductor packaging and test services. The company offers wafer probe, package assembly and design, final test, burn-in and characterization at its manufacturing facilities in Korea and the Philippines. Additionally, wafer fabrication is offered in Korea. Administrative headquarters are located in West Chester, Pa., with offices throughout the U.S., Asia and Europe. [amkor.com]