We are entering an era in which packaging and interconnection will be the prime factors determining performance and the cost of electronics. For the past half-century, the great productivity gains projected by Moore's Law have exploited a steep learning curve in semiconductor technology. Looking ahead, Prof. James D. Meindl of Georgia Tech projects that, "In the future, interconnects will dominate performance and cost; MOSFET's will be secondary." Driven by the demand for better performance, chip designers are moving to CSPs and flip-chips. CSPs are also replacing TSOPs in RDRAM applications because the older packages simply cannot meet electrical performance demands. On larger processor chips, meanwhile, power and ground distribution will drive the explosion in flip-chip I/O. These harbingers of the future foretell a demand for higher performance and lower packaging cost . Conventional chip interconnect is reaching limits due to the increasingly important RC delays that impede transmission in resistive fine lithography. The move to double damascene copper lines and low-k insulators may delay the problem for several generations, while many IC manufacturers look to wafer-level packaging for future interconnect solutions. Expect to see an acceleration of technological
improvements in packaging and interconnect. Many advances will only
be achieved by integrating IC packaging more closely into the wafer
fab, while systems interconnect becomes more closely allied with
chip design.
The Uncompromising demands to further miniaturize microelectronics will bring many new challenges to reliability testing to assure functionality. Quality and reliability issues will be further complicated with moves towards system integration, especially with the inclusion of microscopic moving elements, i.e., MEMS. Even for single-chip packaging, such as CSPs, the use of innovative approaches leads to failure mechanisms not seen in traditional surface mount reliability testing. Today's rapid advances in microelectronics require application-specific test methodologies. Designers must consider reliability concepts during the early stages, not after-the-fact. Manufacturers, as well, must control process parameters effectively instead of relying on inspection/rejection criteria near the end of the manufacturing cycle. Finally, engineers in all disciplines must learn to communicate effectively with one another and with the total scientific community.
The use of copper interconnect technology and reduced features sizes will bring significant increases in operating frequency. In spite of lower operating voltages that are likely to accompany the increase in operating speeds and reduction in feature sizes, I anticipate that thermal management at the package level will become a major concern. Previously, thermal issues were resolved by employing heat sinks or spreaders. However, because of reduced available package area in new CSPs, and other advanced packages, new thermal solutions will be sorely needed. A second area likely to command attention in the next few years is packaging materials. There is no doubt that, in some cases, reliability demands have been lowered for new small packages because current materials are inefficient. New thermoset,thermoplastic and elastomeric materials exhibiting enhanced physical and mechanical properties, i.e., extremely low moisture pick-up, will be needed to provide wafer-level packages that offer the requisite reliability for demanding applications, such as automotive. Greater cooperation between chemists, materials scientists and packaging specialists will help resolve these issues to the betterment of the industry.
Technology advances will spur the growth of 3D interconnects early in this new millennium. These advances will involve not just stackable packages, but the stacking of chips and wafers, as well. Device stacking can materially reduce the distancesignals must travel between chips, which, in turn, can improve performance while reducing product size. Future systems will continue to shrink in size and use less power. They will also need larger amounts of memory as well as higher speed data processing to handle the increasing amounts of data used in video and natural language applications. Future systems are likely to incorporate some type of electro-optical technology. To add emphasis to the growing importance of this technology, Japan has formed the Association of Super-Advanced Electronics Technologies ASET), a new consortium to develop advanced stacking technologies to create new 3D systems.
The recent movement among European countries and Japan towards lead-free solders has at last brought this issue to the attention of U.S.-based industries as well. Until the present, the microelectronics packaging industry had comfortably settled into Pb-Sn solders, and many other materials requirements were built around them. The requirement to adopt Pb-free solders has brought several other materials issues to the surface, including issues associated with the polymeric materials used-especially their ability to withstand high temperatures. The selection of materials that are used in packaging has not necessarily been done in a systematic manner-but rather in an ad hoc manner, thus far. Why has Pb-Sn solder been the material of choice thus far? Perhaps the reasons are historic, rather than necessary. The impending requirement in the new century to become completely Pb-free presents us with both challenges and opportunities. The challenges are invariably associated with choosing an alternative to Pb-Sn that will have all the necessary properties, including long term reliability. Now the opportunity! This is an ideal time to revisit the materials selection issue and attack it in a systematic manner. Unfortunately I do not see anybody taking such an approach at this time. The overwhelming attitude still appears to be, "Tell me what works, and never mind the details." The effort to eliminate Pb from solders should not be seen as an end in itself, but rather the beginning of a conscious effort by everyone towards leaving our environment in a cleaner state than when we found it. This would be an excellent way to begin the 21st century.
Wafer-level packaging of ICs with high performance materials and low cost processes will become mainstream. Wafer-level processing is the key to lowering the cost of packaging; however, there are numerous other challenges ahead. Among them: materials development. Another issue concerns the need for "no flow" flip-chip underfill materials and processes. In a related area, high-performance substrates with microvias and high density wiring are urgently needed. Achieving the needed performance at an affordable cost is not a trivial issue. In the optoelectronics sector, greater use of photonics to drive speed and performance is key. Dense wavelength division mutiplexing is critical for this technology. Finally, system-on-a-chip and system-on-a-package will continue to grow in importance.
During the next several years, the transition from lead-tin to lead-free solders will have a major impact at all levels of the electronics industry. A drop-in replacement for lead-tin would be ideal, but, in reality, a vast range of solders, lead component finishes and board finishes are being investigated. The manufacturability and reliability of all these technologies must be sorted out to determine overall compatibility-not only with the materials, but also with the existing manufacturing infrastructure. Eventually, one or two lead-free solders will emerge as a standard. The choice of lead-free solder(s) will impact semiconductor manufacturers in many ways. Most significantly, many lead-free solders possess eutectic temperatures of 215oC or higher, compared to 183oC for eutectic tin-lead solder. Unless tighter process controls are implemented during board-level assembly, maximum reflow temperatures could increase to 250oC or even 260oC. These conditions will certainly be a challenge for the molding compound, die attach, laminate and build-up dielectric materials suppliers. Alternative lead finishes/solder ball technologies will result in changes for test, burn-in and rework processes.
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