| Near-CSP Employs
Dry-Film Photoresist to Create Package Leads |
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By David
Francis and Linda Jardine, Contributing Editors
Patent Number: 5,976,912
Assignee: Hitachi Chemical Co.
Inventors: Fukutomi et al.
Title: Fabrication Process of Semiconductor
Package and Semiconductor Package
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The patent in this discussion is not strictly
a CSP patent. However, the method of fabrication is of interest
and the resulting package size is only slightly larger than a pure
CSP.
The process described in this patent is designed
to use sheets, strips or a continuous tape. The patent is 39 pages
in length with several variations of the basic process.
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Figure 1 shows the basic process used
in fabricating the package interconnect. A sheet or strip
of copper is used as the base layer, and a nickel layer is
plated on top of the copper to act as an etch stop when the
bottom layer is removed.
Figure
1. Basic lead fabrication process.
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Photoresist
Applied
A dry-film photoresist is applied over the
nickel and patterned to create the package leads. Layers of copper,
nickel and gold are then plated up to become the leads of the final
package. The gold is used for wire bonding. (The vertical dimensions
are exaggerated in the figures to show the various layers.)
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The leaded package is assembled as shown
in Figure 2. The die is attached using a silver-epoxy adhesive
and then wire bonded. The package is transfer- molded to complete
the assembly.
Figure
2. IC attach and encapsulation.
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After sealing, the base copper layer is removed
using a suitable alkaline etch. The nickel layer acts as an etch
stop. The nickel is then removed using a nickel stripper that has
low copper-dissolving power.
In one version, the base copper layer can be
replaced by a stainless steel foil, but mechanical means must be
used to remove this layer.
Solder Mask
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A solder mask is applied to the bottom
side of the molded package to cover the leads, except for
open areas that will be used to attach solder balls. The completed
package assembly is shown in Figure 3.
Figure
3. Base layer removal and bumping.
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This same approach can be used if the die is
bumped. In the example given, the die has gold bumps and is joined
to the leadframe using thermocompression bonding.
Process Variation
Figure 4 illustrates one variation of the basic
process. Instead of plating nickel over the entire surface of the
base copper layer, the dry film resist is applied directly to the
copper.
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The first nickel layer is then selectively
plated followed by the normal copper, nickel and gold layers
described previously. This eliminates the need to deposit
a nickel strip once the base layer copper is removed.
Figure
4. First Ni layer is placed in lead area only.
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In another variation, the plating sequence
is reversed. In effect, the package is built in the reverse order
with the last plated surface being where the solder balls are attached.
The dry film resist is applied to the copper base and then patterned.
The plating sequence is gold, nickel and copper. After plating,
the resist is removed.
Mask Materials
Next, a solder mask is applied. Various masking
materials can be employed, ranging from a liquid sealing resin to
a polyimide film.
One material can be applied by screen printing,
the other by lamination. With film, it is necessary to laser- form
the holes for the solder balls.
In one variation, the polyimide film is pre-punched
with holes corresponding to the solder ball location. This film
is then laminated to the top surface of the leads (the bottom of
the package).
The copper base layer is removed by etching,
and the interconnect structureis inverted for assembly. The die
is attached as described above.
Continuous
Film
This approach lends itself to making the parts
using a continuous polyimide film.
Other variations involve the use of a two-layer
copper polyimide film to provide a continuous strip process.
Due to the small package size, it is possible
to mold the entire assembly as a single block. After the copper
foil is etched away, the block can be separated into individual
packages using a diamond cutter.
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International Interconnection Intelligence
is a market and technology research company specializing in
the semiconductor packaging and interconnection areas. Contact
David Francis or Linda Jardine by e-mail at
iii1@ix.netcom.com or by phone at 650.728.5270. [iii1.com]
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