PATENT NUMBER: 6,246,114 ASSIGNEE: Oki Electric Industry Co. Ltd. INVENTORS: Yoshikazu Takahashi, Masami Suzuki and Masaru Kimura TITLE: Semiconductor Device and Resin Film Mounting large ICs to a substrate with a different TCE can create high levels of stress in solder joints and lead to premature failures. This patent describes a packaging method that greatly reduces the problem. Prior Art The prior art on this patent is the basic Tessera CSP design using an elastomeric spacer between the substrate and the die, and a flip-chip approach that uses an underfill to manage the stress. Both of these approaches are believed to have limitations. The Invention The approach in this patent appears simple, yet should be effective in separating any TCE stress from the PWB, allowing it to be effectively decoupled from the IC. This approach offers the benefit of standard TAB processing; thus, any special processing changes should be small. The IC is formed with Au bumps, and the substrate is standard TAB with inner leads and an extended interconnect surface. The I/O count does not appear to be high because the leads on one side of the substrate are dummy leads only. These dummy leads keep the chip balanced so that it does not peel away from the film.
The chip is encapsulated by flowing a suitable resin into the center chip area. The extended substrate is then bent 180° and bonded to the front surface of the IC with a special elastic adhesive. Straightforward and Inexpensive Solder preforms can be placed on the upward-facing substrate pads, or bumps can be formed on the substrate to which the CSP is to be mounted. The process, as described, is very straightforward and inexpensive. The space between substrate layers is about 1 mm. The region of the TAB where the 180° bend occurs is coated with an elastic resin. If the TAB leads are already Au plated, Au bumps may not be required. Alternatively, the IC pads can be solder bumped. One improvement to the basic package process is the addition of a supporting frame. This can be made of an insulator or metal and can be open (as shown), or closed, depending on the degree of protection desired. Process people will be quick to realize that a weakness in the basic design is the difficulty in achieving solder preform co-planarity if the extended TAB substrate is simply bonded to the resin- sealed front surface of the chip.
The solution to the co-planarity problem is to insert a thin plate between the two layers. This plate can be adhesively attached to the extended substrate before it is folded over. Adhesive is then applied to the front surface of the IC and the substrate and support plate are folded into position. For die in which heat removal is more of a problem, the metal plate can be extended and wrapped around the die as shown in the bottom figure. In this design, the thin U-shaped metal piece serves as both a support plate and as a heat sink. Another Variation In another variation of the basic approach, the package can be designed in an inverted fashion with the front surface of the chip facing up. This variation provides a larger bend radius for the film and eliminates the need for a support plate, since the back surface of the chip can provide a sufficiently flat surface.
In still another variation of the basic design, the substrate can be formed as a multilayer structure, and the second metal layer can serve as a ground/power plane. An opening may be formed in the film, and a solder preform can be used to make an electrical connection to the support plate, if desired.
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