January - February 1999
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Microvia Technology: The Key to Using CSPs
CSPs and microvias go hand in hand: What is the value of high-I/O-density, chip-scale packaging without a high density substrate to connect them?
By Adam T. Singer , IBIS Associates, Inc., Wellesley, Mass.
Abstract: As the need for high-density, handheld products increases, the electronic packaging industry has been developing new technologies, such as chip-scale packaging and §ip-chip assembly, to pack more information-processing functions per unit volume.
Many system designers, however, believe that the circuit board technology to accommodate packages with high I/O densities has not kept pace. Even though printed wiring board fabricators have been developing new, higher-density circuit fabrication methods, the system designers perceive today's advanced technology as unproven, low reliability, and high cost. IBIS Associates applies Technical Cost Modeling in this paper to examine the cost issues of implementing microvia technology.
CSPs and microvias go hand-in-hand: What is the value of high-I/O-density, chip-scale packaging without a high- density substrate to connect these chips? Alternatively, why have a circuit board with ultrafine features if coarse-pitch devices will be used?
Yet, many system designers believe that either CSPs or microvia technology (or both) mean higher system costs. Certainly, it is wise to be cautious about employing new technologies. But if there are proven technologies that can offer system cost reduction as well as system performance improvements and size reduction, what are you waiting for?
IBIS Associates has studied the cost impact of microvia technologies on circuit board fabrication1, and of CSP technologies on IC packaging2. This paper shows some of these cost analyses, revealing the cost savings possible through the use of these advanced technologies.
CSPs and microvias go hand-in-hand: What is the value of high-I/O-density, chip-scale packaging without a high- density substrate to connect these chips? Alternatively, why have a circuit board with ultrafine features if coarse-pitch devices will be used?
Yet, many system designers believe that either CSPs or microvia technology (or both) mean higher system costs. Certainly, it is wise to be cautious about employing new technologies. But if there are proven technologies that can offer system cost reduction as well as system performance improvements and size reduction, what are you waiting for?
IBIS Associates has studied the cost impact of microvia technologies on circuit board fabrication1, and of CSP technologies on IC packaging2. This paper shows some of these cost analyses, revealing the cost savings possible through the use of these advanced technologies.
Methodology-Technical Cost Modeling
Technical Cost Modeling (TCM), a methodology pioneered by IBIS Associates, provides the method for analyzing cost1. The goal of TCM is to understand the costs of a product and how these costs are likely to change with alterations to the product and process.Specifically, TCM includes the breakdown of cost into its constituent elements (listed below), and ranking cost items on the basis of their contribution:
- Materials and energy
- Direct and overhead labor
- Equipment, tooling and building
- Other costs
In short, TCM provides an understanding not only of current costs but also of how these costs might differ in the face of future technological or economic developments.
High-Density Packaging Technologies
Much has been published on microvia technology3,4 and chip-scale packaging5,6. Microvia technology, also called build-up technology, allows high-density circuitry on the outer layers of a circuit board, with lower, conventional-density circuitry on the inside layers.These high-density circuit boards contain a conventional core, for rigidity and cost reasons, among others. Since the materials used in creating microvias tend not to have glass reinforcement, the core layers, which are glass reinforced, provide the rigidity needed for handling and end-use structural requirements.
Creating vias smaller than 6 to 8 mils (150 to 200 microns) in diameter, allows higher-density circuit layers to be created than with conventional technology in general. These vias are created through a myriad of technologies, including the following:
- Advanced mechanical drilling
- Lasers
- Photoimageable dielectric layers
- Plasma etching
Yields
Microvia technologies have been adopted by most large board fabricators and are being used by some OEMs, mainly in Japan. Reported yields achievable with microvia technology range from 50% to 95%, depending on the technology, how long the fabricator has been learning fabrication techniques and many other factors. Further details of each technology are presented elsewhere1.Most §ash memory devices are being offered in CSPs for use in portable electronic products. Uses are on the horizon for many other ICs, but CSPs are just beginning to be employed outside of memory.
In summary, CSPs and microvias have "burst onto the scene" due to the demand for complex handheld products and other compact electronics. Since it can be construed that their implementation is driven mainly by the need for smaller form factors and not by cost, both microvias and CSPs have suffered from perceptions of high cost among potential users.
But is this necessarily true?
When a new technology is introduced, it tends to cost more, with the promise that, eventually, costs will be lower than they are today.This situation occurs because volume production is necessary for costs to come down, and new technologies are usually introduced at low-volume levels. At their beginning, as customers "test the water" these low volumes often do not allow the new technology to cost less than the incumbent technology. This is happening today with CSPs and microvias.
Cost models can show if new technologies will, in fact, cost less at higher production volumes. This analysis shows some of the cost results from recent work at IBIS.
Microvias
| Table 1. Results from Microvia Cost Analysis | |||
|---|---|---|---|
| Conservative Case | Average Case | Aggresive Case | |
| Number of Metal Layers Eliminated | 2 | 2 | 4 |
| (before/after) | 12–10 | 8–6 | 10–6 |
| Board–Area Reduction | 0% | 33% | 75% |
| Microvia Board Dimensions (inches) | 2.2 x 6.0 | 4.3 x 5.3 | 2.0 x 2.0 |
| Boards Per Panel Increase (before/after) | 0% | 33% | 75% |
| (assumes 18" x 24" panel) | 21–21 | 10–16 | 20–80 |
| Number of PTH Vias Eliminated | 334 | 877 | 2,932 |
| Number of Drilled Blind Vias Eliminated | – | – | – |
| Manufacturing Yield – Microvias | 80% | 80% | 80% |
| Minimum Cost Savings (most expensive microvia technology) | –31% | 14% | –5% |
| Maximum Cost Savings (most competitive microvia technology) | 9% | 42% | 75% |
| Average Cost Savings (11 microvia technolgies considered) | –9% | 31% | 57% |
A report published by ITRI (contact Jack Fisher at 512.833.9929) provides a detailed cost analysis of microvia technologies. The analysis in this article shows a portion of the results from that report. More detail is also provided in one of the references1.
Table 1 summarizes the cost savings achievable with microvia technology in a few case studies. For each of these cases, the cost of a conventionally designed board was compared to the cost of this board redesigned for microvia technology.
Out of the eight design case studies in the report, three are shown here, providing different approaches to designing microvias into a system.
When implementing microvia technology, designers have a spectrum of options: On one hand, they can change the board design very little, not affecting the layout or types of packages on the board, only changing the number of signal layers in the circuit board; or, more aggressively, the designer can assume finer–pitch devices, a smaller board, and fewer signal layers.
Table 1 shows two designs at either end of this spectrum and one that is roughly in the middle.
From this analysis, it is evident that microvia technology is likely to enable lower–cost boards than conventional technology.
For the system designer, this raises a critical question: Even though a bare circuit board might cost less, will the system cost less, since "expensive," fine–pitch components are likely to be used on the high–density microvia board?
The next section takes a look at packaging costs.
Chip–Scale Packages
| Table 2. Results from CSP Cost Analysis | ||||||
|---|---|---|---|---|---|---|
| TSOP | Flex with Silicon | Flex with Overmold | Wafer Level (periph.) | Wafer Level (array) | Panel with Thin Film | |
| Lead Pitch (mm) | 0.5 | 0.8 | 0.8 | 0.5 | 0.8 | 0.8 |
| Manufacturing Yield | 99% | 95% | 95% | 95% | 95% | 95% |
| 46 I/O | ||||||
| Die Per Wafer | – | – | – | 366 | 385 | – |
| Die Per Panel | – | – | – | – | – | 289 |
| Die Per Magazine | 40 | 40 | 40 | – | – | – |
| Relative Cost | 1 | 1.5 | 1.4 | 0.6 | 0.6 | 0.6 |
| 144 I/O | ||||||
| Die Per Wafer | – | – | – | 32 | 129 | – |
| Die Per Panel | – | – | – | – | – | 144 |
| Die Per Magazine | 40 | 32 | 32 | – | – | – |
| Relative Cost | 1 | 1.1 | 0.9 | 2.0 | 0.6 | 0.5 |
Through recent projects at IBIS, many advanced IC packaging technologies have been studied. This article shows a portion of the results from these projects.
Table 2 summarizes the costs for a selection of IC packaging technologies, including five types of CSPs as well as the thin, small outline package (TSOP) incumbent. Two levels of leadcounts are provided here, since changing leadcount affects different packaging technologies in different ways.
As shown in Table 2, some CSP technologies cost less than TSOP technology, while others cost more.
Note, however, that this analysis is subject to change as these technologies are developed, and cost positions improved.
From a system perspective, high–density technologies can reduce cost through the combinations shown in Table 3.
| Table 3. Scenarios for System Cost Reduction | ||||||
|---|---|---|---|---|---|---|
| TSOP | Flex with Silicon | Flex with Overmold | Wafer Level (periph.) | Wafer Level (array) | Panel with Thin Film | |
| 46 I/O | ||||||
| Aggressive Microvia | P | P | P | B | B | B |
| Average Microvia | P | P | P | B | B | B |
| Conservative Microvia | L | L | L | P | P | P |
| 144 I/O |
|
| ||||
| Aggressive Microvia | P | P | B | P | B | B |
| Average Microvia | P | P | B | P | B | B |
| Conservative Microvia | L | L | P | L | P | P |
| (B=Best Case, P= Promising, L= Limited Potential for Cost Reduction) | ||||||
Given the cost differences between the circuit boards and the cost disparity between CSP technologies, we can generate conclusions about the number of packages needed for each board to reach cost parity.
For instance, consider the conservative microvia circuit board case, which costs 9% more than the original conventional board. If we assume this conventional board is meant to have TSOPs mounted on it, the system designer might want to know how many wafer–level CSPs are needed on the conservative microvia board to reduce the system cost to parity with the conventional case.
Table 4 provides this analysis, omitting the cost impact of differences in the assembly of packages onto the circuit board. (CSP assembly costs are currently being studied by IBIS Associates, but this analysis is not yet ready to be published.)
NOTE: These results cannot be generalized for other systems; this analysis is unique to this system alone.
Interpreting Table 4
| Table 4. System Cost Analysis (Does Not Include Assembly) | ||||||
|---|---|---|---|---|---|---|
| TSOP | Flex with Silicon | Flex with Overmold | Wafer Level (periph.) | Wafer Level (array) | Panel with Thin Film | |
| 46 I/O | ||||||
| Number of packages needed to offset the cost increase of the conservative case | N/A(no change) | N/A(cost will increase) | N/A(cost will increase) | 6 | 6 | 6 |
| Number of packages needed to offset the cost decrease of the average case | N/A(no change) | 17 | 22 | N/A(cost will decrease) | N/A(cost will decrease) | N/A(cost will decrease) |
| Number of packages needed to offset the cost decrease of the aggressive case | N/A(no change) | 28 | 35 | N/A(cost will decrease) | N/A(cost will decrease) | N/A(cost will decrease) |
| 144 I/O | ||||||
| Number of packages needed to offset the cost increase of the conservative case | N/A(no change) | N/A(cost will increase) | 17 | N/A(cost will increase) | 3 | 2 |
| Number of packages needed to offset thecost decrease of the average case | N/A(no change) | 32 | N/A(cost will decrease) | 4 | N/A(cost will decrease) | N/A(cost will decrease) |
| Number of packages needed to offset the cost decrease of the aggressive case | N/A(no change) | 52* | N/A(cost will decrease) | 7 | N/A(cost will decrease) | N/A(cost will decrease) |
| *52 CSPs will not fit on the top and bottom of this circuit board | ||||||
When implementing microvia technology to redesign a system, the resulting bare board will likely cost less than its conventionally designed counterpart.
When using microvias translates to a more expensive circuit board, it is possible to offset this cost increase by using CSPs that cost less than the packages that were used in the conventional case.
For a specific case where microvias made the cost of the bare board increase by 9%, the cost can be "brought back" to parity with one of the following options (plus many other options not shown here):
- At least six 46–I/O, wafer–level or panelbased CSPs
- At least seventeen 144–I/O, flex with overmold CSPs
- At least three 144–I/O, wafer–level (array) CSPs
- At least two 144–I/O, panel–based CSPs
When using microvias translates to a less expensive circuit board, system cost reduction is assured if CSPs are used that cost less than the packages they replace.
When the microvia–based board costs less than the conventional format, it is also possible to use CSP technologies that cost more than the packages replaced, within limits. For the specific case where the cost of the microvia–based board costs 31% less than the conventional case, the following limits exist (many options, not shown, also exist):
- Up to seventeen 46–I/O, flex w/silicone CSPs
- Up to twenty–two 46–I/O, flex w/overmold CSPs
- Up to thirty–two 144–I/O, flex w/silicone CSPs
- Up to four 144–I/O, wafer–level (peripheral–leaded) CSPs
- Up to twenty–eight 46–I/O, flexx w/silicone CSPs
- Up to thirty–five 46–I/O, flex w/overmold CSPs
- Up to fifty–two 144–I/O, flex w/silicone CSPs (this many packages don't fit on the substrate, so the system can't cost more in this case!)
- Up to seven 144–I/O, wafer–level (peripheral–leaded) CSPs
Summary
From this analysis, it is clear that high–density technologies can not only reduce the size of a system and increase its performance„they can also reduce the cost of a system.Using cost analysis, this article has shown that the cost can be reduced for all three systems that were analyzed, given the use of various CSP technologies. System cost savings could occur, even for those cases where the microvia–based version of the board costs more than the conventional case, if CSPs replace higher–cost IC packaging.
Since these results are unique to the three board designs and five CSP technologies analyzed in this article, these conclusions are not applicable to every system.
In any case, some form of cost analysis should be implemented in the design stage to ensure that system cost is minimized."
References
- A. Singer and R. Bhatkal, "Why It Makes Sense to Use Microvia Technology: An Objective Study of Microvia Economics," Proc. of the 1998 IPC HdI Conference, Nov. 18–20, 1998, Mesa, Ariz.
- A. Singer and T. Hannibal, "Making Sense of CSPs and BGAs Through Technical Cost Modeling," Proc. of Surface Mount International 1998, August 24–27, 1998, San Jose.
- M. Andrews and J. Fisher, "ITRI's 'October Project': The Microvia Center of Competence," Future Circuits International, Vol 1, Issue 1
- H. Holden, "Micro–via PCBs: The Next Generation of Substrates and Packages," Future Circuits International, Vol 1, Issue 1,
- J. Vardaman, "Chip–Scale Packages: Cleared for Takeoff," Chip Scale Review, May 1997, p. 8.
- K. Wesselmann, "CSPs and the Portable Electronics Age," Advanced Packaging, February 1998, p. 52.
Mr. Singer, also a project manager at Ibis, received a bachelor's degree in mechanical engineering from the Massachusetts Institute of Technology. Since joining Ibis in 1992, he has led projects in microvia technologies for high–density PWBs, chip–scale packaging and other areas involving advanced IC packaging. Contact him at atsibis@aol.com or by phone at 781.239.0666.