January - February 1999
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NEC Patent Addresses High I/O Applications
By David Francis and Linda Jardine
International Interconnection Intelligence, Montara, Calif.
Patent Number: 5,757,078
Assignee: NEC Corporation
Inventors: Shuichi Matsuda and Kazutaka Shoji
Title: Semiconductor Device with Increased Multi-Bumps and Adhered Multilayer Insulating Films and method for installing same.
Conventional CSP designs have several limitations that make them less desirable for high I/O applications where bump size must be made smaller and placed closer together. Some of these limitations are:
- An increase in the noise level
- Increasing probe difficulties
- Increasing reliability problems
- Inability to replace if underfill used
Probing is a problem because the solders typically used for solder bumps form oxides on the surface. As the bumps are made smaller, it becomes increasingly difficult for the probes to penetrate this oxide and make good contact to the bumps without damaging them. The force applied by the probe to make good electrical contact can damage the bumps.
As the bumps are made smaller, the distance between the IC and the substrate becomes less, and this reduces the ability of the bump to withstand stresses caused by any TCE mismatch which results from materials or temperature variations.
If an underfill material is used to improve reliability, it becomes difficult to repair or replace the device if it is subsequently found to be defective.
Construction
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| Figure 1. CSP with higher I/O capability and other enhancements |
The interconnect structure is designed to redistribute perimeter pads to area-array bumps.
Reduced I/O Metallization Pattern
The metallization pattern of the two- metal-layer polymide film is designed to reduce the number of I/Os required and, at the same time, reduce the amount of noise.Figure 2 shows a portion of the top and bottom layers of this pattern. The top figure shows the routing from the IC pad connections to the vias that go through the film to the bottom metallization pattern.
Insulating Layer
The lower pattern shows the use of a large ground plane that covers most of the bottom surface except for the signal and power connections. An insulating layer is applied to the surface to keep any excess solder from shorting to this ground plane.The use of a large ground plane substantially reduces the number of package I/O required. An additional benefit is that the via connections to the ground plane can be made at locations that do not interfere with the normal package I/Os. This results in a further improvement in I/O utilization.
Probe Method
As bump sizes become smaller, it becomes more difficult to make reliable electrical contact to them without damaging the bumps.The solution proposed in this patent is to make the probe contact a series of very small bumps that are able to penetrate the surface oxide of each bump, but not sufficient to cause any substantial damage. As shown in Figure 3, the size of the probe bumps is such that from 3 to 5 bumps make contact to each solder bump.
A Stronger Solder Bump
As the number of I/Os increase, the bump size and pitch must be made smaller. Due to the stresses incurred during temperature cycling, the reduced pad size was found to be the cause of solder bump failure where it joined the pad.The solution proposed in this patent, and illustrated in Figure 4, is to plate the copper pads of the interconnect film to form enlarged Cu pads as shown. The solder forms a much stronger bond to this large pad and is better able to withstand the environmental stresses.
Improved Assembly and Repair Method
The bumped surface of the interconnect layer of the CSP is coated with a thermoplastic resin as shown in Figure 5.When the CSP is placed on a substrate and re§owed, the solder bumps wet to the substrate pads to form the electrical connection. The thermoplastic resin then softens and completes the assembly process by encapsulating the bump and forming an adhesive bond to the substrate surface. This resin functions as a repairable underfill and eliminates the need to perform a separate underfill step.
The device can easily be removed from the substrate by heating to re§ow the solder and soften the thermoplastic resin. It may not even be necessary to clean the site after the removal, although this can be easily done.
International Interconnection Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection areas. Contact David Francis or Linda Jardine by e-mail at iii1@ix.netcom.com or by phone at 650.728.5270.
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| Figure 2. Reduced I/O metallization pattern | Figure 4. Stronger solder bump |
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| Figure 3. Improved probe method | Figure 5. Repairable attach method |