By
Jerry Secrest
Secrest Research Do CSPs compete with known-good die, or does one complement the other? You could assume that they are competitors, but it is the application that determines whether known-good die (KGD) or chip-scale packaging is employed. KGD is the right choice for the highest density and performance. In applications where low cost, moderate density and §exibility are required, however, CSPs are the choice, but both are needed now. Status Report CSPs are generally deÞned as a package about 1.2X the dimension (1.5X the area) of the die. Within this definition, CSPs have many variations. However, a trend among manufacturers is the move towards wafer-level or frame processing, which allows several to many die to be processed into CSP packages in an array. The CSP is then tested in the array format and singulated. Both methods support reduced manufacturing costs. KGD has been around for almost a decade, but KGD testing and processing is still evolving. The concept is that KGD will have the same electrical specifications, quality and reliability as die in packages. KGD are in bare die form for use with wire bonds and with ball grid arrays, or C4 arrays for §ip-chip attachment. In the last few years, KGD suppliers have been pressured to upgrade the testing to make higher quality KGD. This pressure is being applied by manufacturers of mobile, low-cost products, such as cell phones and personal digital assistants. CSPs have incomplete standards to cover their manufacture and resulting "package." Manufacturers have their own variations in packaging, manufacturing methods and testing, because a significant proportion of CSP manufacturing is for internal consumption. An issue with KGD is the package outline, since a change to the die is also a change to the package. If a semiconductor company performs a die shrink, package outline changes cause handling requirements to change. If the die employs wire bonds connected to the leads on a substrate, a die shrink will need a different bonding program. A shrunken KGD with BGA connections may or may not cause the BGA to change. Meeting Spec Another KGD issue is how to assure that the IC meets electrical speciÞcations and reliability requirements when testing is done in die form on a wafer. Part of this issue can be addressed by wafer testing at both low and high temperatures. High temperature testing is needed because CMOS performance declines as temperature rises. This testing can be cost effective because wafer probers rapidly index die to the test head. Stress testing is performed at wafer test to accelerate the failure of a die that may fail in early field life. Some semiconductor companies are using wafer-level burn-in to remove early life fails. Still another technique employs data modeling to predict failure-prone die. Teammates Let's consider for a moment a stacked CSP (SCSP), which is a multi-chip module disguised as a CSP. Packaging for SCSPs begins by stacking two or three die on top of a BGA substrate with an insulating strip between them. Leads are bonded to the substrate, and molding around the stack completes the device. Since a SCSP is a package that may even be smaller than the enclosed die area, our deÞnition of a CSP no longer holds. An SCSP example is paired Flash memory and RAM. Another SCSP is memory to support logic. These stacked packages are so thin (1.4 mm), that wafers must be thinned to 150-200 microns prior to wafer saw for die separation and placement. Special die sockets are needed if test or burn-in is performed after wafer saw. Test Yields Achieving high SCSP test yields requires internal KGD with matched speed performance, i.e. the same speed grade. If the die speed grades do not match, the enclosed chip combination will be unuseable. Speed testing is typically done on product after packaging,but SCSP needs are pushing product speed testing back to wafer test. An additional issue is the diagnostics of SCSP test failures. Diagnostics are made difÞcult because there are fewer connections to the package with SCSPs than if the enclosed die were in separate packages. A solution to this problem may be to modify the design of the circuits on the die to allow for diagnostics. E-Test KGD test may include high and low temperature function testing (at speed) and sometimes wafer-level burn-in. An alternate to speed testing is the use of E-test to bin wafers by speed grade. The KGD test moves complete product testing in front of packaging. Die exiting from KGD test can go into either MCMs or SCSPs and then be tested for the packaged function. (Alternatively, this die may be used in single-die packages, requiring only a test for opens/shorts to ensure a viable packaging interconnect.) The bin data from E-test (and or KGD test) is transferred to the die-attach location to selected wafers (and/or die) to match the required speed grade. Wafers not suitable for KGD §ow can be screened out at E-test and routed to conventional packaging that includes full testing plus burn-in. Near-Term Impact Because the industry needs die tested to KGD criteria for high SCSP test yields, KGD and CSP are teammates in providing a cost-effective solution for the OEM. Once semiconductor companies accept KGD testing to meet MCM and CSP needs, they may start to test all product by this method to reduce after-packaging test time and costs.
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