Though typically removed from wafer processing, it is useful for the packaging community to be aware of the changes that are taking place in the wafer fab. One major change that has taken place is, of course, the integration of copper interconnects on the wafer. It has been three years since IBM announced the use of copper interconnects in its advanced chips. Since that announcement, other semiconductor companies and wafer foundries have followed suit with their own plans to employ copper metallized wafers. As expected, this change in interconnect material and accompanying processes has attracted the attention of equipment and material suppliers worldwide. In the next few years, new developments will emerge as chipmakers learn how to process copper interconnects for devices with critical dimensions of 100 nm and smaller. Interconnect Structure The successful integration of copper interconnects in fabs is dependent on the processes used to form the dual damascene structure. Dual damascene refers to an interconnect structure where the metal is deposited into vias and lines already patterned into the underlying dielectric. Any "excess" metal deposited above the vias and lines is polished off the wafer. As a result, copper-filled lines and vias can be formed without a messy copper etch process. In fact, the industry has never discovered an acceptable dry or wet etch process for copper, so the dual damascene structure has allowed fab engineers to clear a critical barrier in fabricating copper interconnects. Deposition Techniques The dual damascene line and via structures are filled by electroplating copper onto the wafer. Electroplating is a new process for fab engineers, although it's a process both the packaging and printed circuit board industry is quite familiar with. Electroplating can successfully fill high aspect ratio (height/diameter) vias. It is also reportedly a less expensive technique than sputter or chemical vapor deposition (CVD). Both sputtering and CVD processes, however, play an important role, and will continue to do so, in the overall copper process flow. Sputter deposition has not disappeared-at least for the time being-with copper interconnects, but its application has certainly evolved. Historically, sputter deposition has been the workhorse process for depositing aluminum, and it is a technology that has been extended further than once thought possible for submicron features (a familiar scenario in chip manufacturing).
For the current generation of copper interconnects, a sputter process is used to deposit, first, a thin barrier material, which prevents the copper from interacting with neighboring layers and the silicon device itself, followed by a thin copper seed layer. This layer is needed for electroplating the thicker copper interconnects. Enhanced sputtering tools are necessary to sputter deposit these seed and barrier films. Both Applied Materials, Santa Clara, Calif. [appliedmaterials.com] and Novellus, San Jose [novellus.com] offer enhanced deposition tools that result in a high level of ionization (up to 90 percent), of the sputtered atom. By applying an electrical bias to the wafer, the sputtered, ionized atoms are deposited uniformly, and with good step coverage, across the wafer. Target utilization, i.e., more wafers processed per target, also improves with these enhanced tools. CVD equipment and materials suppliers are anxiously waiting in the wings for the time when (or if) sputter processes run out of steam, as critical dimensions continue to shrink. Meanwhile, processes are being developed for copper seed layers and barrier films, with the expectation that CVD for these metals will be required at the 100 nm device generation. Barrier Metals It has also become apparent that the titanium nitride barrier films used with aluminum will be replaced with a new material for copper. The early frontrunner is a tantalum nitride film, but other materials are also being considered (see table). A number of factors will come into play in selecting which barrier materials will be used as interconnect geometries shrink. Though sputtered tantalum nitride has been successfully integrated into the process flow, there remains an all-important cost-of-ownership concern with this material. Intricately designed tantalum targets, used in advanced sputtering tools, can be expensive-reaching $40,000 or more for some target configurations. Prospects for lowering the tantalum target costs are dim, considering that the base metal price climbed in the past year. Thanks to strong demand for the metal in the capacitor market, tantalum is now priced at $47/lb, up from $30/lb just a year ago. A version of aluminum's titanium-based barrier film may eventually be integrated with copper, or perhaps a chipmaker will use an entirely different barrier material.
Copper Alloys One material change that could directly impact packaging engineers would be the use of copper alloys on the wafer.
The aluminum metal used on most chips is not a pure aluminum, but an alloy with either silicon or copper. Alloying is necessary to improve the mechanical strength and the reliability of thin aluminum interconnects. Pure copper does not form a nice, self-passivating native oxide like aluminum; thus, it is highly susceptible to oxidation, even at low process temperatures. A protective, self-passivating layer can be formed on copper by alloying with aluminum, magnesium, titanium or another element. Alloying also helps improve adhesion and other reliability-related properties of the copper interconnect, although alloying could impact wirebonding, and, perhaps, wafer bumping processes. The semiconductor industry's transition from aluminum to copper will pick up steam in the next 1-3 years for advanced logic chips and microprocessors. Additionally, aluminum technology will likely remain strong in the memory market for the next 3-4 years. Interestingly, the copper revolution has coincided with the advent of wafer-level packaging, which, for several schemes, requires a copper redistribution layer across the wafer. Packaging engineers will also become experts in processing copper on wafers thanks to these emerging wafer-level technologies!
|
|||||||||||||||||||||||||||||||||||||||||
Copyright © 2001