By Terrence E. Thompson, Senior Editor
Flip-chip packaging is at a crossroads. Mainstream acceptance depends on the correct answers to a few vital questions. Perhaps the key to this acceptance depends on when the technology, substrates and interposers are able to be produced at competitive costs. It's apparent that wafer-level packaging and RDL approaches do, indeed, simplify the production of flip chips. Yet, understanding the many variables-including process and material issues-is still a task of the highest order. Generally, flip chips are ready for prime time. Yet, newcomers are puzzled and frustrated by terminology, design and production issues. Workable Combinations Some flip-chip packages are available in quantity now at low-to-moderate I/O counts and volumes. How to choose a workable flip-chip package variant for a given application is not always obvious, however, especially for higher I/O counts. Selecting the "right" combination means striking a balance between well-understood processes, materials and equipment infrastructure and stepping into an abyss of unknowns. It may also require investing in new materials and equipment ,and even bringing in knowledgeable subcontractors to perform some, if not all, process steps. Wafer-level flip-chip packaging promises to dramatically lower device costs. The wafer-level process can redistribute flip chip I/Os to match other device or substrate I/O pad pitches and layouts. It can also help with many other challenges by making certain that the under-bump metallurgy is in place for conventional or lead-free materials. WLP can deliver solderable UBM pads, RDL, pre-bumped flip chips and encapsulated flip-chip packages. (Several examples of flip-chip bonders are shown in figures throughout the article.) New to Flip Chips? Are you new to flip-chip processing? Although most ICs are still surface-mounted devices, the number of flip chips is increasing. If you need to learn how to use them, it gets interesting fast. You must make a distinction between new and experienced users, says Dr. George Riley, president of flipchips.com.
Dr. Riley adds, "New users must still hack through an information jungle to learn what flip chips are-and why there are 57 different varieties." He adds that even some expert users face significant challenges in understanding newer materials and working with new applications.
Dr. Tom Di Stefano, president of Decision Track, agrees. "Information is fragmented right now for new users, especially material sets." He believes the key flip-chip and wafer-level challenges boil down to dealing with two fundamental problems, the first involving larger die sizes. Current wafer-level packages, he observes, are primarily used for small dies with low I/Os. The challenge is to improve reliability beyond 3mm die sizes, and to deal with TCE mismatches between the die and its substrate. To Redistribute or Not? A second challenge comes with higher I/Os, adds Dr. Di Stefano. "Beyond 20 I/Os, you probably need RDL. That layer is relatively expensive compared to other packaging options, so the flip-chip challenge is to expand beyond 20 I/Os inexpensively." Flip chips for low I/Os do not need RDL, making it very cost effective. "We actually see RDL as a growth area," says Dan Mis, vice president of applications engineering and design for Unitive. "If you're looking at RDL purely for wiring or moving I/Os, then it's fairly expensive." You can increase value with wiring, Mis says. "By adding inductors, making large power and ground planes, it becomes a more cost-effective process." Mis says that Unitive is seeing real RDL growth for wiring and multi-level wiring technologies as a package application, not just for relocating I/Os. Cells, the Next Big Driver "One important thing to remember, at least with flip chips, is that flip chips are a technology," says Richard Groover, vice president, at Amkor's flip-chip products business unit. He emphasizes that flip chips are not a package type. "It's a process and theoretically can go into any package, although that's not likely to happen." "We have five different flip-chip products in production at Amkor now, with 17 to 20 package variations. The most exciting one is flip-chip MLF (Microleadframe). When we go beyond 2.5G and get into 3G phones, those applications will drive incredible growth in flip-chip packages." Dr. Di Stefano agrees that cell phones will drive flip chips. "Another very exciting possibility is flip-chip memory parts in WLP format. It's little more than a flip chip dressed up as a package, but it offers enhanced reliability and greatly simplifies test and burn-in." Before this becomes a reality, however, higher volumes and better standardization are needed, he says. Holy Grail "We look at memory as the holy grail of wafer-level CSP," says Unitive's Mis. "It looks like a package and acts like a package, but it's just a chip joined to the board, so no underfill is needed." Flip chips, we hasten to add, are not for semiconductors only. "I see non-IC applications-MEMS, optronics and biomedical flip chips-coming on strong," says Dr. Riley. Keep in mind, however, "Some optronics users want to work at up to 350°C with flip chips," he adds. An aspect related to memory, points out Amkor's Groover, is combining wire bonds with flip chips in stacked packages. "Today, this is driven by memory and ASIC types of die combinations."
With ICs increasingly joining MEMS in the same package, "The other holy grail is a true hermetic cavity WLP for MEMS," contends Dr. Riley. "A few patents exist and there has been continuing development," he says, although he's unaware of any available production WLP with a true hermetic cavity. "There's great interest in hermetic cavity WLP for MEMS, but the holdup is the sealing technology," he says. "You need the vacuum, sealing and cleanliness at the same time. An odd difficulty found in a micro-cavity package is the difficulty in determining hermeticity. "You can't use the mil specs because the cavity volume is too small," Dr. Riley notes.
Needed: Simpler Flip-Chip Roadmaps Scott Barrett, Marketing Director at the Flip Chip Division of Kulicke & Soffa says the Kulicke & Soffa unit has qualified a flip chip package for a DRAM supplier. "However, current technology versus wirebond is cost prohibitive." While reliability issues can be resolved, RDL designs are not as cost competitive as wire bonding, he adds. Until DRAM producers accept a simplified flip-chip design roadmap, volumes at the mainstream level will not take place, says Barrett. "For instance, we're focused on the high-temperature bumping market and programs that drive down costs to make it more mainstream." How Much Is Too Much? Using WLCSPs, customers face the same issues with chip-scale versions of DCA devices that they saw with wire-bonded versions, contends Amkor's Groover. "Customers want multiple vendors supplying the same footprint. Cost is an issue and what they want is full turnkey capability where the supplier offers WLP design, WLP processing through electrical test, die sort and shipping to their customers." Flip-chip CSP and flip-chip MLF are performance-driven applications, he adds. "If we can get costs down, then you'll see widespread adoption of flip-chip packaging in the marketplace."
That's fine for volume, notes Riley, "But what about people that eventually will be high volume but cannot find anyone to help them develop at the prototyping threshold?" One nearly universal question from users involves development at the prototype stage. How and where do you find it? That's where K&S' Flip Chip Division, Unitive and other bumping houses come in, says Groover. "We get many low-volume die in wafer form that were processed at bump houses. We perform electrical test, dicing, short inspections and die plating and then put the devices on tape and reel."
Cohesive Coordination "The major challenge is cohesive coordination between wafer fab, bump house and assembly/test house," K&S' Barrett insists. "It's very difficult for merchant suppliers to control the wafer fab. If you're Intel, you control the wafer fab and the bump fab in the same facility." The industry, explains Barrett, "Is still learning how to design for flip chip from the IC through wafer fab, bump and assembly." How we reach that apex, Barrett adds, is not clear yet. "Many chips were not designed just for flip chip. But they want interchangeability between wire bond and flip chip-something that becomes problematic. Does This Flip Chip Work? This is an ongoing, vexing question. Just when chipmakers seemed to have KGD issues under control, those irascible flip- chip upstarts changed the equation. It is more cost-effective to test at wafer level and then sort good and bad die. However, producing the same die with differing UBMs, pad patterns and pitches quickly becomes a nightmare for chipmakers. What makes much more sense is to deliver whole wafers, with the KGD identified, to users or contract manufacturers to perform the WLP. As wafer-level packaging gains momentum, chipmakers reluctantly are accepting the fact that actual yields and device performance variations will become public knowledge.
Conclusion Although many challenges exist for using flip chips, the supply chain pieces are falling into place. WLP flip chips are gaining momentum with new world-class capabilities coming online around the world, especially in Asia. The virtual flip-chip factory is likely an imperative. Products, and the chips that enable them, are being developed and deployed very quickly. Volumes may be modest initially, and it is unlikely that most companies will have the know-how, expertise and production capabilities to make everything themselves. New product introductions make last year's products less attractive (or obsolete), so most volumes will remain modest. Contract manufacturers and service providers may well be the glue that holds it all together. Yes, there are many flip-chip variants. Using them with appropriate substrates and interposers, as well as picking the assembly/packaging materials for the task, requires doing your homework. Generally, flip chips are indeed ready for prime time, but most users will find partnering with specialized subcontractors well worth considering. |
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