March 2003 The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging Email the editor

Terrence E. Thompson Senior Editor

Ziptronix Inc., a start-up in Research Triangle Park, N.C., boasts a unique, room-temperature, covalent wafer bonding process. It's also fast at under a minute (just ask anyone that uses other wafer bonding techniques). So far, so good.

The company employs familiar wafer processing, packaging gear and chemicals. Yes, the process does require a clean room environment, roughly class 10. So what makes this process so special, and why did it take 10 years to figure it out? The devil lies in the lack of process sequence details. Additionally, the proprietary surface-activation process is covered by several patents that disclose little.

Ziptronix spun off from the Research Triangle Institute (RTI), and commercializes the Institute's bonding technology. RTI invested a decade of R&D (with a little federal funding) into the ZiROC bonding process.

The process, says Ziptronix, simplifies fabrication and packaging integration of MEMS, high-speed logic, opto, RF devices for wafer bonding and true 3-D device fabrication. The process supports both wafer-to-wafer and die-to-wafer-level bonding.

This shows die-to-wafer bonding in action where a donor die is placed in a waffle pack and then bonded to a host wafer.

Covalent Bonding?

This primary bond process involves one or more atoms sharing a pair of electrons. Each of the two atoms supplies one of the electrons. ZiROC's availability corresponds nicely to some emerging trends in the IC packaging arena that make better bonding timely.

One trend is the use of thinner wafers and devices followed by a not-too-surprising increase in stacked chips for a functional 3D sandwich. The other trend is adding micro- and nano-scale optical and mechanical functionality by using photonic and MEMS devices in the same packages with virtually any type of IC. Opto and MEMS devices do not tolerate much heat without failing.

With ZiROC opto or MEMS bonding, you can literally put a lid on it-be it a transparent window layer for photon transmission or just a lid to keep it clean. When done, just dice them like regular wafers for packaging.

J. Douglas Milner

Secrets Disclosed!

Everyone loves a good mystery, especially Ziptronix' chairman, president and CEO J. Douglas Milner, the man with the sly, knowing grin on his face. When we spoke recently, he politely declined (again) to furnish "Colonel" Milner's secret recipe, but his general explanation is intriguing.

"Over the past ten years of basic material research, we developed a simple solution for achieving clean room-ambient, room temperature covalent bonds. Materials are planarized using conventional back grinding and CMP followed by wafer and/or die surface activation using standard fabrication chemical processes," Milner says.

He also insists there is nothing special about the wafer fab or high-speed pick-and-place equipment used for die-to-wafer bonding alignment.

Doug says virtually invisible interface covalent bonds form between the materials in intimate contact without using adhesives.

There is the special sequence of surface conditioning steps, which is their trade secret. It could be that they are simply taking advantage of some short-lived phenomena that typically are overlooked with longer intervals between process steps in other approaches. Timing could be everything here since it is a fast process.

Standard Via and Metallization

Once bonded, each die or wafer layer can be thinned to about 10µm, exposing the backside of the thinned material's active components. Standard via and metallization techniques will interconnect layers, and the resultant 3D structure is placed in industry-standard packages.

The technology does not employ adhesives, and the chemicals used do not remain on the wafers. Covalent bonding is compatible with a wide variety of dissimilar materials, since the CTE problems found with high-temperature bonding are avoided.

Custom Substrates

Ziptronix now supplies bonding and interconnect services, including custom engineered substrates, low-cost, wafer-scale, hermetic MEMS encapsulation and 3D integration of virtually any semiconductor device. Xilinx, San Jose, is one Ziptronix investor (and likely customer).

SMI silicon micromachined, piezoresistive pressure-sensing MEMS chip

Will the Ziptronix process go mainstream? Only time-but not Doug-will tell.

Major MEMS Facility Expansion

Just when many are wondering about the IC, opto and MEMS recovery, Silicon Microstructures Inc., Milpitas, Calif., is bucking the "wait-and-see" trend with a major expansion and renovation of its recently purchased MEMS wafer foundry.

SMI has relocated some silicon etch operations from its Hawthorne, Calif., facility to Milpitas. The company is also upgrading the infrastructure and purchasing new equipment to add capacity for its expanding pressure sensor and MEMS foundry business. [si-micro.com]