Dr. Makato Shinohara On Encapsulation: An Expert Looks At The Issues

Since 1987, Mak has worked for Ciba Specialty Chemicals as technical director and industrial manager for active device packaging products. He divides his time between Ciba's of fices in Southern California and Japan.

Prior to joining Ciba, he was technical manager for Morton Chemical Company's Polyset Group in Woodstock, Illinois. Earlier, Mak was a senior research chemist at Dow Corning in Midland, Michigan. He holds bachelor's and master's degrees in polymer chemistry from the Tokyo Institute of Technology and two Ph.D. degrees in physical chemistry from the State University of New York, Syracuse, and from Syracuse University. He also holds numerous patents, mostly in polymer synthesis and molding compounds, has written many technical papers and is a member of the American Chemical Society.

Q Why is the encapsulant important to chipscale packaging?

A The success of chip-scale packaging (CSP) depends greatly on its design as well as on the assembly equipment and materials used. An encapsulant plays an important role as the principal assembly material, putting a chip and an interposer, leadframe or leads together to create a semiconductor assembly. Further, it protects the device from mechanical, physical, chemical, electrical and dielectric environments. The encapsulant used also greatly influences the device's compatibility with the packaging process and equipment and will affect manufacturability, productivity, assembly cost and device reliability.

Q What are the basic selection criteria for an encapsulant?

A The encapsulant must fill a cavity, gap or space with ease, and should not leave any voids when encapsulation is complete. It must adhere firmly to the surface of a chip, interconnects, leads, leadErame, interposer (substrate), and/or soldermask. Dimensional stability during exposure temperature, humidity and various chemicals is another important requirement of assembly materials. Furthermore, a combination of assembly equipment, assembly process and the encapsulant must be commercially fit, providing for as short an assembly cycle time as possible.

There is a sign)ficant mismatch of the coefficient of thermal expansion between silicon die, interconnects, leads/leadframe, interposer, and soldermask. An encapsulant must dissipate shear stress to avoid device warpage while protecting the chip from failure due to pinpoint stress, corrosion, intermetallic growth or the popcorn effect during board assembly.

Different encapsulants will exhibit different properties and performance and will influence the success of CSPs, just as different encapsulants influence TQFP, TSOP and many other plastic packages.

Q What trends do you see in materials for packaging?

A Quite a few designs have been developed for chipsize packages aiming to secure a position in the market place. Assembly materials and methods which are used for traditional plastic packaging of semiconductor devices (including the BGA), are often applied to the assembly of such chip-size packages. Tessera's µBGA® package is different in this regard because it employs a new silicone based adhesive and a flexible polyimide interpose as well as a new assembly approach.

Efforts will continue in the coming years to find new designs, assembly materials, processes and equipment. New and enhanced combinations will provide smaller and lighter semiconductor packages at a reduced total packaging cost with flexibility, productivity and reliability. For certain CSPs, underfill will be used to boost the reliability of solder joints between the CSP and PWB.

Q What package formats will become popular?

A The overmolded chip-scale BGA will gain in popularity over the coming years because of its low total assembly cost, flexibility, reasonable reliability and performance. In such an overmolded package, a die is mounted with a standard die attach adhesive onto a flexible polymide substrate, then gold wire is used to provide interconnects to the I/O. Traditional transfer molding with an encapsulant completes the packaging process. For high-speed and high 1/O packages, flip-chip technology will be combined with the overmolded chip-scale I1BGA and the die will be flip attached to an interposer. An underfill will be used to protect such interconnects. Preapplied underfill or other cost-effective means will replace today's liquid underfill for cost and productivity considerations.

Q What are the challenges in developing new CSP encapsulants?

A A successful encapsulant for CSPs must deliver the following properties and performance: (1.) Flowability into narrow gaps and openings without leaving voids or air pockets, (2.) Optimal wetting to the chip surface, interconnects, leadframe, soldermask and substrate for desirable adhesion, (3.) Cure profile for productivity and manufacturability, (4.) Low shear stress for reduced warpage and pinpoint stress with minimal filler sedimentation, (5.) Reliability under steady or cyclic stresses from temperature and humidity, (6.) Compatibility and flexibility with selected assembly equipment and processes and (7.) Low total assembly cost. These requirements share many of the attributes of a traditional encapsulant.

Q What are the key issues involved in the development of CSPs?

A Among the key issues is the absence of standardization in chip-scale packaging, as well as rapidly changing equipment and materials requirements. Different semiconductor companies are developing different designs for chip-scale packages with virtually no standardization. Various assembly equipment is being developed for enhanced productivity, the equipment's compatibility with an encapsulant is vital for successful CSP assembly. Shrinking dies for higher speed and lower cost are making such standardization very difficult for chip-size packages as well. Furthermore, performance requirements often change to accommodate frequently-amended specifications.

Q What do you view as the solution to the above standards dilemma?

A The development of the infrastructure through an alliance among semiconductor companies, assembly materials suppliers and equipment manufacturers is indispensable to the successful development and commercialization of chip-scale packages.

Q How will CSPs fare vs. traditional plastic packages?

A As a general trend, semiconductor devices will become increasingly smaller and lighter for increased portability and speed. The PBGA and TQFP formats will be used more than the PQFP format, while CSPs will be used more frequently than TQFP, TSOP and PBGA formats, in new applications where compactness and speed are important. CSPs will create new applications and will increase their share among various semiconductor package types. Forecasts estimate that about 20% of total semiconductor devices will be packaged in some type of CSP (including BGA) by the year 2003. However, the availability and cost of the interposer or substrate, as well as standardization, will greatly affect the growth of CSPs within the semiconductor industry.