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CSP Standards Impact PC Board Design
By Vern Solberg Tessera Inc., San Jose, CaliforniaThe development of chip-scale packaging enables many of the goals for smaller product size to be achieved; however, the circuit structure for mounting and interconnecting the smaller CSP devices can be more complex than those used for leadframe-type plastic devices to meet user demand.
Many CSP concepts are already in production from companies attempting to meet the industry's requirement for smaller overall product size. Companies supplying these devices must also consider the end users' concern for package standards and compatibility with conventional PC board fabrication and assembly technologies.
CSP StandardsSeveral CSP families have been approved by JEDEC and EIAJ. To help in defining a universal acceptance for the CSP device category, both organizations are working to establish guidelines for developing future device standards. The 0.50 mm pitch array device, for example, described in JEDEC document MO- 195, is a uniform square-package outline with a maximum height limit of 1.20 mm.
JEDEC specifies a nominal contact diameter of 0.30 mm, and the optional depopulation of contacts within the array matrix is permitted. Of course, silicon die is seldom uniform in shape, and the contact pitch, as well as the number of contacts required for each device interface, must be considered.
The EIAJ Chip-Scale BGA Design Guide describes packages using an interposer structure with the contact diameter increasing as the array pitch spacing expands from 0.40, 0.50, 0.65 and 0.80 mm. Many U.S.-based chip-scale-device developers, however, are recommending a common 0.30 mm contact diameter for all contact pitch variations. Furthermore, as a practical solution for packaging memory, companies are adapting a wider contact pitch to enable circuit routing. Flash memory devices have already reached the market with a 0.75 mm contact pitch, and soon, DRAM and SDRAM packaging will be available with an 0.80 mm contact pitch (Figure 1).
Figure 1 - Memory devices have been introduced by several leading manufacturers. The Flash memory is available in 48 I/O array with 0.75 mm pitch, while DRAM and SDRAM devices with 60 and 90 I/O have adapted 0.80 mm contact pitch.
Other issues that must be considered by companies supplying a commodity market include the overall size of the device and the pin-for-pin compatibility between device families that have similar functions. Planning by these manufacturers can be critical to accommodate revisions or refinement of the die design. The silicon may undergo several changes, improving performance or reducing the area of the die (die shrink), but if the die size changes radically or the bond sites are rearranged, compatibility between earlier product offerings may be compromised.
Design and Fabrication IssuesRigid multilayer laminate structures will continue to be the primary material for surface mount applications; however, component and circuit routing density for CSPs is significantly higher than for circuits using leadframe-type packaging. Therefore, several trade-offs must be considered: Adding more circuit layers may allow for lower circuit density, but the added layers may increase the thickness of the substrate, raise fabrication complexity and drive fabrication costs higher. On the other hand, finer circuit lines and closer spacing, while reducing the need for added circuit layers, may prove to be more costly as well, if reasonable fabrication yield cannot be maintained.
Package developers creating a true chip-size package are restricted as well. When determining the array matrix for a package no larger than the die outline, the space reserved for the contacts may be limited to an area slightly smaller than the die outline. PC board designers must consider circuit density as well as the physical structure of the substrate. Contact size, spacing and ball alloy material are also significant factors when planning the circuit structure. The interface contact or grid is typically arranged in a uniform column and row format, but the package material and specific alloy furnished on the contact sphere is not always described by the supplier.
Land Pattern DevelopmentThe attachment site (or land pattern geometry) recommended for fine-pitch CSP devices is circular, with the land pattern diameter matching or adjusted to be slightly smaller than the sphere diameter. Land pattern sites can be etched copper patterns with solder mask just outside the pad perimeter, or they can be solder-mask defined.
In the mask-defined pattern, an opening in the mask is slightly smaller than the etched copper pad. The finished condition of the solder joint profile may be influenced by the presence of soldermask on the attachment site. A land pattern that is free of mask material, for example, will generally promote a uniform tapered slope or column-shaped profile, while the mask-defined land pattern promotes a slight collapse of the ball profile during reflow processing.
Circuit Routing for Array DevicesCircuit density for miniature fine-pitch array devices is typically higher than that defined for the larger pitch plastic BGA. Signal routing channels on the outer layers of the PC board will be restricted by the space reserved between land patterns or via-pad sites. To provide the most efficient circuit routing for more complex devices, the inner or subsurface circuit routing may be considered for a majority of the signal paths. To maximize fabrication yield and control board costs, fabricators recommend, when possible, the use of wider signal lines and spacing between features (Figure 2). To accommodate the precise geometry needed for fine-line, chip-scale applications, suppliers may also recommend adapting thinner copper foils or foil clad laminates.
Figure 2 - Devices with a common 0.30 mm contact diameter and 0.75 or 0.80 mm contact pitch provide a practical path for circuit routing. When routing fine-line circuit paths between land patterns, the designer must consider fabrication process capability and limitations of specific suppliers.
The designer may choose a more robust clearance by adding more circuit layers, but when the design demands higher density circuit routing with finer line width and closer spacing, the board becomes more difficult to manufacture, which often increases overall product cost.
Fine Line/Circuit Layer Trade-offFiner lines and spaces, while reducing the need for added circuit layers, may prove to be more costly due to a lower fabrication yield. Alternative fabrication techniques are available for preparing the interconnect structure, and they may prove more practical and economical for specific applications. Adding circuit layers to the rigid PC board may increase fabrication cost, but multilayer construction with via holes drilled and plated through all circuit layers is generally more economical than the sequential process steps needed for blind or buried via holes.
Drilling and plating small via holes can drive up fabrication costs too, but lamination of all layers can be completed in one step. Before adapting blind or buried vies, consult the fabricator and consider the cost trade-offs between sequential lamination and standard lamination incorporating smaller via holes and pads and finer lines and spaces for the circuit routing.
Complexity Rating for PCB Fabrication Even smaller blind-via holes can be made using laser drilling; however, the process is slower than spindle drilling, requires specialized equipment, and because boards are typically laser drilled one-up rather than stack drilled, unit cost may be significantly higher. Chemical or plasma drilling of small or micro-via holes is also a consideration. The most economical method of small, blind-via hole formation uses photoimaging and plated-via technology. In any case, the surface area reduction possible using one of the high density fabrication technologies will prove dramatic and may meet cost objectives for the finished product as well.
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