Defining CSP Pitch Standards Was a Controversial Task

By James Hayward
Contributing Editor

When BGA packages were first proposed to JEDEC, the only ball array then tooled was at a pitch of 1.50 mm. The deliberations within the JC-11 committee that resulted in the issuance of the first BGA registration, MO-151, extended the pitches for the BGA family to 1.27 mm and 1.0 mm. The 1.0 mm pitch was the smallest pitch defined, largely because of the perceived limitations of PC board technology. The committee believed that for mainstream usage, the 1.0 mm pitch was the practical limit for PC board design and manufacturing.

At finer pitches, the routing of conductors into dense arrays of solder balls would be very difficult, and production of the BGA substrates themselves would likewise be difficult. Of course, the ball array configuration provided such a significant increase in contact density over alternate packages that users would, so the experts assumed, require some time to utilize the increased capability fully.

Birth of the CSP

This illustration compares the Type 2a, Type 2b and "real" chip-size packages.

If anything is constant in the electronics industry, however, it is that satisfaction with the status quo is impossible. Thus, almost as soon as BGA packages began to appear on the market, efforts began to develop smaller, finer pitch versions and the chip-scale package was born. Historically, the interest in chip-scale packages-and the BGA versions in particular-grew first in the United States and Japan. The reasons for this interest, however, were different in the two countries.

Japan's interest was spurred by the miniaturization of consumer products, such as video cameras, and was focused on logic and ASIC devices with some consideration for DRAMs.

In the United States, however, the flash memory producers displayed the most eagerness to learn about CSPs, and their interest was directed mostly toward the telecommunications industry. The activity in both countries arose independently, and, as a consequence, resulted in significant problems for standardization.

The first problem was to define the pitches for BGAs below 1.0 mm. The first chip-scale BGA that was proposed to JEDEC featured a pitch of 0.50 mm and otherwise followed the format of the MO-151 outline. There was fairly universal agreement with this pitch choice, but the difficulty arose with attempts to define intermediate pitches, if any, between 1.00 mm and 0.50 mm.

The argument in favor of intermediate pitches was that PC board technology was not widely available to accommodate a pitch as fine as 0.50 mm. Initially, JEDEC leaned toward a single intermediate value of 0.75 mm. However, the EIAJ proposed to apply an "80% rule," resulting in two intermediate pitches: one at 0.80 mm and another at 0.65 mm (0.8 is 80% of 1.0 and 0.65 is 80% of 0.8, etc.).

The difference became a source of serious discussion during the annual EIAJ/JEDEC joint meetings held in 1995 and 1996. While the standardization discussions were ongoing, many Japanese manufacturers were tooling CSP BGAs at 0.80 mm pitch, and the major flash memory manufacturers were tooling packages at 0.75 mm and 0.65 mm.

"Significant Difference"

There was a significant difference between the two camps because flash memory development focused on the "real" chip-size (see figure) BGA packages (described as type 2b in an earlier column), while the Japanese developments were largely, but not exclusively, focussed on the fixed body size BGAs (type 2a).

The distinction in product type and package type gave rise to a compromise on standard pitches, which was first proposed at an EIAJ/JEDEC task group meeting in December 1996. That compromise has subsequently been followed by both organizations in defining the standards for Ūne-pitch BGAs.

Both organizations agreed on 0.50 mm pitch and were leaning to include 0.65 mm as an intermediate pitch. The disagreement settled on the choice of 0.75 mm or 0.8 mm. EIAJ argued for 0.80 mm on the basis that board routing would be easier. JEDEC argued for 0.75 mm, based on the need for smaller ball array areas for flash memory packages.

Final Agreement

The final agreement ultimately recognized both arguments by accepting 0.75 mm as a standard pitch for the type 2b packages, defined by die size, and 0.80 mm as a standard pitch for type 2a packages. Thus, the standard pitches for FBGAs are a function of package type and, indirectly, package function.

For fixed body size FBGAs (type 2a), the pitches would be 0.80 mm, 0.65 mm and 0.50 mm. For chip-size FBGAs for memory applications (type 2b), the standard pitches would be 0.75 mm, 0.65 mm and 0.50 mm. EIAJ has also proposed 0.40 mm as an additional pitch, but the proposal has sparked little interest.

Package Definition

JEDEC has defined the type 2a packages in the registered outlines MO-195, MO-205 and MO-210. Type 2b FBGAs are defined in MO-207. The general requirements for square body FBGAs appear in a section for the Design Requirements Standard, JESD 95-1, that is awaiting publication after being approved by the JEDEC Council. General requirements for rectangular type 2a and 2b packages will be covered by additional sections of JESD 95-1 that are currently being drafted.

(JEDEC package outlines are avail-able on the JEDEC Website at www.jedec.org/download/freestd/pub9.)

Mr. Hayward is a senior member of technical staff in the Manufacturing Services Group at Advanced Micro Devices (AMD), Sunnyvale, Calif. He has been the AMD member of the JEDEC JC-11 Committee since 1982 and was instrumental in developing the JEDEC outlines for BGA, PGA and TAB packages. Mr. Hayward can be reached at james.hayward@amd.com or by phone at 408.982.6427.