Japan Prepares for a New Era in IC Packaging

By Prof. Tadatomo Suga
University of Tokyo

Last year will be regarded as an epoch-making one for IC packaging research and development in Japan, due to the establishment of a consortium (The Institute of Advanced Microsystems Integration) by Japan's leading semiconductor companies. Until 1998, the R&D in this specialty area of electronics was typically carried out by individual companies within the industrial sector. Earlier, Japan was nearly alone among developed nations which did not support an electronics packaging consortium.

Formerly, only infrequent attention was given to IC packaging research and subsequent follow-through by academic institutions. Now, as the consortium moves into its second year, major changes in packaging R&D are taking place.

History

In the autumn of 1996, ten of Japan's largest OEMs/semiconductor makers began to discuss the establishment of a consortium to promote IC packaging-related R&D. (The original 10 have since been joined by several others.)

Corresponding to this action by industry, MITI (Japan's Ministry of Internal Trade and Industry), through its Electronic Device Section, launched an advisory committee for electronic systems integration in October 1997.

The committee members included the consortium members, as well as PWB makers and components suppliers. This committee, which I chaired, submitted an interim report in March 1998.

The report summarized the critical issues in IC packaging technology, especially opto-electronics system integration and packaging, three-dimensional, high-density interconnection and system integration and environmental safety issues.

Product Engineering

It is in the area of production engineering that Japanese industry has been recognized and praised for both its production control and for the thoroughness of its engineers.

Technology advancements have been made in the past because most large semiconductor makers have supported their own R&D departments with enough staff and money to pursue forward-looking technologies.

With business conditions in Japan, like most of Asia, in a recession—especially for the semiconductor segment—the need for R&D in advanced IC packaging become even more critical.

System LSI, which requires a combination of logic and memory devices, is an area in which the Japanese need to demonstrate expertise at production engineering.

"System-on-a-Chip"

For high-speed and high-performance LSI, the "system on a chip" is the final goal. However, these diminutive systems confront engineers with severely demanding tasks.

One of the most difficult requirements is the need to design the interconnection between functional blocks, and this

interconnection often represents an obstruction to realizing maximum system performance.

Concurrent Design

The multichip module approach, which makes the most of the transmission line structure of the printed circuit board to mount LSI chips, may still provide an answer for low-cost requirements.

This solution requires a concurrent design concept, including a seamless relationship between chip design, packaging design and system design.

The good news is that the chip-scale package format can be adopted to build an effective MCM, pending a long-term solution to the difficult job of testing high speed LSI in the bare die format.

Next generation packages, which we will refer to as "system packages," can only be realized by enabling high density and fine pitch interconnections at the same level of on-chip interconnection, and also by establishing innovative technology. This future technology may be comprised of three-dimensional and/or optoelectronic interconnections.

A Japanese word "jissoh," which does not yet appear in Japanese dictionaries, but can be translated as "mounting," is commonly used by industry to describe chip interconnection, mounting, assembly and packaging—as well as the implementation of technologies in hardware and software from the component level to the system level. This implementation assumes workable spatial and functional boundary conditions with minimum costs.

The new packaging R&D drivers result from the reconsideration by industry of how to develop the system package concept and how to exercise the potential of the system integration business.

Dr. Suga is a professor at the University of Tokyo's Research Center for Advanced Science & Technology and a leading architect of Japan's semiconductor industry. He received a master's degree from the University of Tokyo in precision engineering and a doctorate in materials science from the University of Stuttgart, Germany. Contact him at suga@pe.u-tokyo.ac.jp, phone +81-(0)3-3481-4487 or fax +81-(0)3-3481-4586.