Media Kit
For advertisements and demographics
click here
Current Advertisers
 Publisher's Letter
Everybody Talks About Customer Service

 Assembly Lines
The MQUAD Package Is a Survivor, but Its Future Is Still Cloudy

 Wafer-Level Watch
Packaging Will Fuel the Productivity Engine of the Future

 Harvey Miller's Notebook
'Irrational Exuberance' Ended in 2000 - for Awhile, at Least

 Industry News
EtroniX Brings Rain but Few Smiles in Anaheim; NEPCON Replacement Struggles for an Identity
MEPTEC/CPMT SiP Event Brings Packed House
Company News
People in the News
Packaging Foundries
Calendar of Events
Editorial Index

 Features
Testing Integrated RF Devices: Keeping Ahead of the Technology Curve
The Squeeze Is On! Designing Sockets for Next-Generation IC Packages

Socket Vendors

An Expert Looks at the Issues: Paul Sakamoto On Final Test

Special Report: CSPs in Europe - A New Attitude

 Tutorial
Burn-in Sockets for Chip-Scale Packages

 Technical Forum
How Heat Sink Size, Ambient Air Temperature and Air Velocity Affect IC Burn-in

Solder Joint Stress in a Cavity-Up, Flex Based BGA

Effects of Pb Contamination on the Material Properties of Lead-Free Sn/Ag/Cu/Sb Solder
 Tools & Technologies
Phoenix Intros 3D X-Ray Inspection System and more...

 Patents
This Simple Wafer-Level Package Offers High Reliability at Low Cost

 Archives
2001
Jan-Feb March April
May-June July  
2000
Jan-Feb Mar-Apr May-June
July-Aug Sept-Oct Nov-Dec
1999
Jan-Feb Mar-Apr May-June
July-Aug Sept-Oct Nov-Dec
1998
  Mar-Apr May-June
July-Aug Sept-Oct Nov-Dec


Subscription

 
Current Issue
An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics
April 2001

Solder Joint Stress in a Cavity-up Flex-Based BGA

ABSTRACT
Solder joint reliability is an issue with many fine-pitch area-array assemblies, including rigid and flex-based BGAs and flip-chip directly attached to PWBs, due to the CTE mismatch between the silicon die and circuit board. With flex circuits, the incorporation of a laminated copper stiffener with a CTE close to the PWB creates a cavity-up, enhanced BGA (CUEBGA). Cross-sectional moirŽ interferometry, coupled with finite element analysis (FEA) of the assembly, indicated low solder joint stresses, much like the improvement made by underfilling flip-chips. FEA incorporated several experimentally determined material properties to obtain better agreement with the moiré results, then explored different package materials. FEA showed that a recent change to a softer lamination adhesive should result in lower stresses and, therefore, improve reliability.

By Guotao Wang and Dr. Paul Ho, University of Texas (Austin); Drs. Terry Hayden and Eumi Pyun, 3M Electronic Products Division, Austin; and Dr. Douglas Gundel, 3M Fiber Optics and Electronics Technology Center, Austin

Since the early days of IBM's controlled collapse chip connection, (C4)(1), solder joint reliability/thermal fatigue in solder array assemblies has been a critical factor because of the CTE mismatch between the silicon die and the carrier. The following general formula approximates the maximum possible shear strain in the flip-chip-on-board construction(2):

(1)

CTEi = coefficient of thermal expansion for the die or board

ΔT = temperature range of the stress cycle

DNP = distance from the neutral point of the solder joints

H = die-to-board standoff height

In reality, the resistance of the solder joints to deformation reduces their strain below this level with larger solder joints offering more resistance. Because modern devices are migrating toward fine-pitch (which limits solder joint size) and toward larger sizes (which increases DNP), this equation indicates limitations for the FC-on-board construction.

Figure 1. Flip-chip assembly. The die has been directly attached to a multilayer printed circuit board (PCB) carrier with underfill surrounding the solder joints.

One solution to reduce the solder joint stress and increase reliability in FC solder joints is to underfill the solder joints(2,3) (Figure 1), but this is not desirable for many solder array assemblies, because it requires additional process steps and limits rework.

BGA packages, whether based on conventional rigid substrates or higher-routing-density flex circuits, may also suffer from similar board-level reliability issues, but a package offers a significant opportunity for reduction of these stresses through an increase in the package CTE.

Figure 2. Cavity-up enhanced ball grid array (CUEBGA) package that incorporates a stiffener laminated with adhesive to the polyimide flex circuit

Package geometry and materials selection can dramatically affect these solder ball strains, and hence reliability. For example, a CUEBGA (Figure 2) differs from a conventional flex-based package, such as Texas Instruments' µStar or Amkor's fleXBGA4 by incorporating a copper stiffener that is laminated to the flex circuit prior to assembly (Table 1)(5,6). It also differs from other package constructions that provide a relatively thick compliant layer between the die and the solder balls (such as a thicker die attach adhesive(7) or elastomer as in µBGA™), to reduce the solder ball strain, or others that alter other geometrical factors such as the solder ball pad size(7).

Improved Handling and Reliability

This addition improves handling during first-level assembly manufacturing(6), enhances heat dissipation(5) and results in an increase in the overall package CTE to better match that of the PWB(5,6).

End-user reliability testing has recently demonstrated that the 12 mm CUEBGA package construction with stiffener meets tough telecom equipment attachment reliability requirements (two-parameter Weibull characteristic life of 6300 cycles for 0 to 100°C stressing(7)).

In previous CUEBGA studies, moiré interferometry of this package by itself (not mounted to the board) proved useful for experimentally determining that its CTE was close to the PWB(5,6). In the present study, cross-sectional moiré interferometry was employed to determine stresses and strains throughout the package in board-mounted devices.

The measured solder ball stresses were then compared to three dimensional package FEA. The results of this investigation are given below. They suggest that there is an opportunity to decrease solder ball stresses further through the judicious selection of adhesive materials in the construction. A low modulus adhesive8 selected for use in this package has the required high-temperature durability for package fabrication and service, as well as the requisite properties for low solder ball stresses.

Table 1. Thickness of CUEBGA Package Components (µm)
Overmold (above die) 500
Die 250
Die Attach Adhesive 25
Copper Stiffener 125
Flex Substrate 50
Lamination Adhesive 50
Solder Ball Diameter 800
PCB 1570

Solder Ball Stress Analysis

Moiré interferometry is a whole-field optical interference technique with high resolution and high sensitivity for measuring the in-plane displacement and strain fields9. Recently, this method has been used to measure the thermal-mechanical deformations of electronic packages with the objective of studying electronic package reliability(10). Figure 3 shows the optical system of moiré interferometry.

Figure 3. Optical system for moiré interferometry

Standard moiré interferometry employs a grating frequency of 1200 lines/mm, which yields a spacing of the interference fringe corresponding to 417 nm of in-plane displacement. While the sensitivity is adequate for measuring the overall thermal deformation of electronic packages, it is not sufficient for measuring thermal deformation in high-density electronic packages-particularly for small features such as solder balls. For this purpose, high-resolution moiré interferometry was developed based on the phase shifting technique.

In this study, high-resolution moiré interferometry was carried out, in addition to the standard interferometry, using an IBM PEMI (Portable Engineering Moiré Interferometer) which was modified for phase-shifting operation. The detection sensitivity for phase-shift moiré interferometry can reach 26 nm per fringe(11).

Package Analysis

Moiré analysis was carried out for the 12 mm CUEBGA package with 0.8 mm pitch that had been reflowed to a two-layer PWB and cross-sectioned. A schematic of the 12 mm CUEBGA package with the two sections that were analyzed is shown in Figure 4. (Section 07 and section 45 correspond to the seventh (middle) solder ball line and the diagonal solder ball line respectively.)

Figure 4. Schematic of the 12 mm CUEBGA package

Each specimen was cut and polished to the mid-section of the solder balls. A low-viscosity, brittle adhesive was selected to adhere a 1200 lines/mm grating on the cross-section of the specimen at 102°C. This adhesive was chosen to reduce the adhesive thickness (and hence the shear-lag effect). The deformation at this temperature was taken as a reference (zero) deformation state. The experiment was performed at a room temperature of 22°C, thereby providing a temperature change of 80 degrees centigrade (ΔT= -80°C).

Finite Element Analysis

Three-dimensional FEA of the 12 mm CUEBGA package was performed using commercial FEA software(12). FEA was first used to duplicate the same sectioned sample as the moiré results and then used to analyze the entire package. Due to the symmetric structure and deformation, only a quarter of the package was modeled. Temperature-dependent elastic-plastic properties for eutectic solder were input in the model.

Initially, all other materials but the solder were considered to be isotropic linearly elastic. Without considering the plastic property for the die-attach adhesive, the FEA result did not agree with the moiré result. For this reason, a micro-tensile system was employed separately to measure the stress-strain relationships for the die-attach, polyimide, and the proprietary adhesive.

In this system, two computer-controlled encoder stepper motors are used to generate static sample displacements of less than 1 micron, and a load cell provides data for determining the applied load. The stress-strain curves generated by this system for the three adhesives were then input into the FEA model.

Figure 5. U-field (top) and V-field (bottom) moiré fringe patterns for section 45

Results

An example of a moiré fringe pattern is shown in Figure 5, which also includes a superimposed outline of the interfaces. Results from both section 07 and section 45 were similar. A number of qualitative observations regarding the package deformation can be made from the patterns:

  • The overall deformation of the package (U and V fields) is that of bending.

  • Both the U and V displacement fields exhibit relatively small displacement gradients across the copper-solder ball and the solder ball-PWB interface, which indicates that the copper layer is effectively shielding the solder balls and the PWB from the die.

  • The outermost solder ball has the highest normal and shear strains in comparison to the others, as is evidenced by the higher number of fringes and the inclination in the V field. This may be due to the fact that this solder ball lies outside the projection of the die.

  • A critical area is the die-copper interface, especially at the die corner, as evidenced by the fringe mismatch across this interface.

(a)
Figure 6. Average (a) normal and (b) shear strains in the solder balls for section 07(0 corresponds to the central and 6 to the outermost solder ball)
(b)

Critical Findings

The critical findings relative to the solder joint reliability are the solder ball strains. Figure 6 (a) plots the average normal strains in solder balls. εx is approximately constant in all the solder balls and it is about -0.1 percent. The εy displays a somewhat varying value. The outermost solder ball has the highest εy and it is equal to approximately -0.4 percent. The shear strain is given in Figure 6 (b). The two components of the shear strain are plotted separately in addition to the shear strain, εxy.

 Next
 
Copyright © 2001