Packaging is often disparaged as a no-value-added operation. Nano-second speeds and sexy new functions of the latest ICs aren't improved by wrapping the chip in plastic goo that can only create reliability headaches-or so goes the conventional wisdom. This timeworn view is finally changing in response to wafer-level packaging, something that promises to change the game in backend assembly. While IC chips continue to turn in dazzling productivity gains by extending Moore's Law indefinitely into the future, packaging has been stagnant for decades at one cent a pin. Since the last downturn, packaging has slipped below one-half cent a pin, as costs are wrung out of the supply chain by moving production to low-cost areas such as China. Paradigm Shift With the advent of wafer-level packaging, the paradigm is shifting profoundly from one-at-a-time mechanical assembly to mass fabrication directly on the wafer. This shift enables cost reduction based on a learning curve much like that enjoyed by the IC industry with the introduction of the planar process four decades ago. Jack Kilby and the late Dr. Robert Noyce replaced the mechanical assembly of transistors with a batch process for making whole wafers full of transistors. First used on small die, wafer-level packaging is moving rapidly into the mainstream. These early ICs are simply small flip-chips dressed up as surface mountable packages that provide adequate reliability. For small die, the thermal mismatch between a silicon chip and its circuit board substrate is insignificant because of the small distances involved. This simple wafer-level package is propagating rapidly across the low end of the product lines at Dallas Semiconductor, IRC, National Semi-conductor, Vishay and others.
The challenge of extending wafer-level packaging to larger die sizes is being pursued aggressively across a broad range of technologies. The next step in this direction is to increase the mechanical flexibility of the solder connection to accommodate a larger thermal mismatch. Already, several suppliers, including AIS/ APack, IZM/Technical University of Berlin, Germany, and Motorola have all emerged with stacked solder balls that promise adequate board-level reliability for large die sizes. Many others are also getting ready for wafer-level production. The more attractive wafer-level technologies use batch processing to make a full wafer of interconnect elements. These integrated processes allow rapid learning and an associated cost productivity based on wafer-processing costs, rather than on cost per pin. Significantly, most batch-oriented approaches are adapted toward using the mature wafer-processing infrastructure to get to market quickly. While the reduction of packaging cost drives early adoption, the integration of backend processing is far more important in the long run. WLP's Strong Potential We are only beginning to see the potential for wafer-level packaging to reduce test costs, to speed time to market and to add enabling functionality to IC chips. Each of these factors is becoming more critical to competitive IC production as conventional protocols run into limitations. Testing consumes a larger and larger portion of total chip costs as complexity increases, and distribution of power and ground to the chip is increasingly difficult as speeds increase and switching voltages decrease. Packaging at the wafer level offers a great opportunity to rethink the backend and to integrate functions to solve growing bottlenecks in design, burn-in, test, handling and logistics. In this new paradigm, packaging has a major role to play in fueling the productivity engine of the future.
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