By Dr. Luu Nguyen, Nikhil Kelkar, and Hem Takiar, National Semiconductor Corporation, Santa Clara, California The proprietary micro SMD, which is surface-mount compatible and employs a standard 0.5- mm pitch, maintains the benefits of a die-size footprint and flip-chip-like interconnects without requiring underfill. National Semiconductor has successfully introduced the micro SMD, a wafer-level chip-scale package (WLCSP), for an expanding number of analog products. The micro SMD is well-suited for the next generation of lighter, smaller, and faster devices targeted for portable applications. With a standard 0.5-mm pitch, the package is surface-mount compatible, while maintaining the benefits of a die-size footprint and flip-chip-like interconnects without requiring underfill. This paper will provide the board-assembly guidelines for the micro SMD, together with some recent board-level reliability data. These guidelines are based on internal tests, solder joint shape modeling and OEMs' assembly experiences with the package. The major factors considered are bond pad design, thickness of screen print, thickness of solder paste, assembly sequence and reflow conditions. Construction Wafer-level chip-scale packages (WLCSPs) have received much attention lately because they offer a complete packaging solution with the same form factor as solder flip-chip direct-chip attach without using underfill.1, 2, 3 Furthermore, WLP reduces time-to-market and inventories, and promises to yield savings in logistics cost control. The proprietary micro SMD is a WLCSP, offering a die-sized package answer that extends flip chip to standard surface-mount technology. The die is designed directly for the flip-chip configuration, with solder balls bumped at 0.5-mm pitch. This pitch allows the package to leverage the existing surface-mount infrastructure without forcing OEMs to move into the more expensive build-up and microvia substrates typically required for flip chip. Standard pick-and-place equipment can readily be used on components with a 0.5-mm pitch. The eutectic Sn/Pb balls are 0.130 mm high, with an average diameter of 0.170 mm. Lead-free versions of the micro SMD are currently under evaluation. Information on package construction, process flows, and solder joint reliability has been presented elsewhere.4, 5
Board Assembly Board Pad Design: When designing the PC board land patterns for the micro SMD, the landing pad size on the PC board side should be between 1x to 1.2x the solder ball pad diameter on the package side (0.150 mm). This design ensures a symmetric, barrel-shaped solder joint, which is necessary for optimal thermal cycling reliability performance. Recommended copper pad and solder mask dimensions are shown in Figure 2 for both non solder mask-defined (NSMD) and solder mask-defined (SMD) options.
Suggestions are 0.160 mm ±0.01 mm round copper pad dimensions and 0.350 mm for solder mask openings with NSMD boards. For SMD boards, the recommended option is 0.175 mm ±0.025 mm solder mask opening, with 0.150 mm as a minimum. The assembly and reliability data presented in this article were collected on the basis of an NSMD design, although no significant differences are expected when these data are used with an SMD design, as long as the solder mask opening is at least 0.150 mm. SMD layout is mandatory for build-up/ micro-via technologies, due to limitations on the minimum copper-pad size. Thickness of Stencil Print Due to the thermal mismatch in silicon and organic PC boards, it is essential to maximize the solder-joint standoff to achieve optimal reliability under temperature cycling conditions. Correct stencil design is the key to ensuring maximum solder paste deposition without compromising the assembly yield from solder joint defects (e.g., bridging, extraneous solder spheres, etc.). Solder Volume For the micro SMD, a 300-µm x 300-µm aperture on a 125-µm-thick stencil provides the necessary solder volume. Apertures on the stencil are offset relative to locations of the landing pads on the PC board to ensure maximum separation between the solder paste deposits, while minimizing the risk of solder bridging. Additionally, laser fabrication, followed by electro-polishing, is essential to generate tapered walls with a smooth surface finish that facilitates consistent solder paste deposition. Chemical etch stencil fabrication is not recommended, because it creates hour-glass-shaped apertures resulting in non-uniform solder-paste deposition across the PC board. To achieve high reliability in temperature cycling, tall solder joints are needed to provide the compliance necessary to withstand thermally induced shear stresses. An additional volume of solder is printed in the form of solder paste using standard solder paste printing operations. Based on the stencil design mentioned earlier, a 100-µm (approximately) thick brick of solder paste can be printed on the PC board. Solder paste also acts as a tacky medium that holds the micro SMD in place during the early phase of the solder reflow operation. During assembly, the solder paste must be kept from drying out, since that will cause solder wetting problems from the absence of flux. Components can also be displaced or even blown away (e.g., by a hot-air knife), due to the absence of a tacky force. The time period between solder paste printing, component placement and reflow must be kept to a minimum. With adequate solder paste, self-alignment will tolerate a certain degree of offset placement.
Assembly Sequence Assembly on the PC board includes process steps similar to those of any other surface-mount component. The micro SMD should not be mounted on the PC board side that is subjected to the wave- solder process. During pick-and-place operations, the force exerted on the micro SMD package should be less than 50 gm/bump to prevent damage to the component and solder bumps. Placement height should be programmed to account for the micro SMD thickness, so that the micro SMD is firmly placed on the printed solder paste without exerting excessive force on the bumps. When old chip shooters are used for component placement, they can induce intrinsic vibrations that may impact accuracy and yield. In that case, the micro SMD components should be placed at the end of the placement cycle to minimize misalignment. The bump surface of the micro SMD is typically flat, due to deformation by the flat-tip probe cards used during electrical test. This flat bump tip ensures coplanarity within ±15 µm-ideal for the standard surface-mount attachment process. Reflow Conditions Standard convection or IR reflow process and equipment may be used. To obtain uniform solder joints with acceptable wetting of the solder bump with the solder paste requires maintaining a reflow temperature above 183oC for at least 60 seconds, but not more than 120 seconds. Adequate time above 183oC will separate flux from solder spheres and eliminate voiding. The micro SMD can withstand up to a 260oC peak reflow temperature and is qualified at JEDEC Level 1. Rework Procedure The micro SMD can be reworked like a standard BGA or CSP, as long as the rework process duplicates the original reflow profile. The following automated procedure was developed using a commercially available BGA rework system and includes localized convection heating with profiling capability, bottom-side preheat, and part placer with image overlay alignment. Manual rework is possible by preheating the PC board to approximately 125oC, followed by removal of the micro SMD from the board by heating it above the solder melting temperature (183oC), using a hot-gas nozzle. Temperature ramp rates must be controlled to minimize damage to other components. Above the melting temperature, the component can be picked up with Teflon-coated tweezers. Once the part has been removed, the landing pads should be heated to melt residual solder, which can be removed by vacuum, hot-fluxed copper coupon or hot-braided copper strip.6 The no-clean flux is subsequently applied to the reworked site. The new micro SMD part is placed and reflowed with the hot-gas nozzle. More details regarding rework equipment and setup have been presented in the literature.7 Key assembly information is summarized in Table 1.
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