An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics July - August 2000 Email the editor

Solder Joint Shape-Modeling

Modeling of the solder ball shape is also carried out with Surface Evolver to complement the assembly design guidelines. Surface Evolver is an interactive program for the study of surfaces shaped by surface tension and gravitational energy, squared mean curvature, user-defined surface integrals, or knot energy.

The program handles arbitrary topology, volume constraints, boundary constraints, boundary contact angles and crystalline integrands expressed as surface integrals. More information can be found in a recent study evaluating the shape of joint formation for wafer-level flip-chip underfill processing.⁸

		Figure 4. (a) Schematic of micro SMD with screen printed solder paste before and after reflow; (b) Final standoff heights as a function of initial solder paste height predicted with Surface Evolver
(a)	(b)

Figure 4(a) depicts a simplified schematic of a solder ball on a micro SMD contacting the solder paste screen which was printed on land pad during pick-and-place.

After reflow, the solder ball adopts the familiar truncated barrel shape, with a final standoff height governed by the total amount of solder and the pad dimensions on both die and board.

Inputs to Surface Evolver include, in this case, the pad dimensions, the volume of solder, the surface tension of solder in flux (both at assembly and reflow conditions), die size (weight) and contact angles. Figure 4(b) illustrates the effect of paste heights on the final package standoff. This information is useful for selecting the proper package standoff for optimal solder-joint reliability.

Standoff Height

A representative crossection of an 8 I/O bump joined to an FR4 substrate is shown in Figure 5(a), which shows the standoff height achieved for the device. Within the geometric confines described earlier, Surface Evolver predicts a solder ball height of 145 µm when a 125-µm layer of solder paste is pre-printed on the board. The shape and height simulated agree closely with the actual standoff obtained, as shown in Figure 5(b).

(a)	(b)
Figure 5: (a) Cross-section of an 8 I/O bump micro SMD bonded to a substrate; (b) Solder joint shape prediction for the micro SMD at 125 µm thick printed solder paste; cross-section of a solder ball of an 8 I/O micro SMD

Solder-Joint Reliability

Solder joint temperature cycling reliability of the micro SMD is assessed per IPC-SM-785 ("Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments").

An 8-bump daisy-chain test vehicle is mounted on a 4-layer FR4 PCB (0.062" [1.5 mm] thick). Two test conditions, namely, 0 to +100^oC, 1 cycle/hr and -40 to +125^oC, 1 cycle/hr. are used. Additional mechanical testing included 3-point bend test, vibration test, and 750 mm drop test per PC Card Standard. The latter results were reported earlier.⁴

Table 2 lists the specifics of the test vehicle and the board used, with results listed in Table 3.

The 8 I/O flip chip configuration refers to the test vehicle without solder paste. A standoff larger than 125 µm can be achieved with the use of a 100-µm thick stencil. At such ball height, the 8 I/O device can pass 800 cycles of -40 to +125^oC and over 2,300 cycles at 0 to +100^oC.

The typical failure mode observed is a fracture in the bulk of the eutectic solder, with cracks typically emanating near the package side. Additional tests are performed at -40 to +125^oC to establish 1,000 cycles of failure-free performance.

Table 4 lists the results of changing the thickness of the screen-printed solder to build up the ball height for taller and more compliant joints.

Conclusions

This article presents general assembly guidelines for the micro SMD package and some recent board-level reliability data as a function of standoff heights.

The micro SMD meets the need for a low-cost, minimum-sized package that can be easily tested on a wafer and readily assembled with current SMT technologies without using underfill. Added advantages include lower cost as wafer size increases or, alternatively, as die size decreases.

Acknowledgments

The authors acknowledge the assistance of National Semiconductor's Analog Products Group, Santa Clara.

References

1. P. Garrou, "Wafer-Level Chip-Scale Packaging (WL-CSP)," Chip Scale International, Wafer Level Packaging Summit, Paper D, 1999.

2. J. H. Lau and S. W. R. Lee, Chip-Scale Package, McGraw Hill, 1999.

3. J. H. Lau, Low-Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw Hill, 2000.

4. L. Nguyen, N. Kelkar, et al., "Wafer-Level Chip-Scale Packaging-Solder Joint Reliability," Proc. IMAPS, 1998, pp. 868-875.

5. N. Kelkar, H. Takiar and L. Nguyen, "Micro SMD-A Wafer-Level Chip-Scale Package," IEEE Trans.On Advanced Packaging, to appear in May 2000.

6. L. Nguyen, P. Fine et al., "Reworkable Flip Chip Underfill-Materials and Processes," Proc. IMAPS Int. Symp. on Microelectronics, pp. 707-713 (1998).

7. P. Wood, "A Successful Rework Process for Chip-Scale Packages," Chip Scale Review, Vol. 2, No. 4, 1998, pp. 41-45.

8. L. Nguyen and H. Nguyen, "Solder Joint Shape Formation under Constrained Boundaries in Wafer Level Underfill," IEEE 50th Electronic Components and Technology Conf., May 2000.

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