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Current Issue
An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics
May - June 2001

Composite Ceramic Substrate Minimizes Microcracking
David Francis and Linda Jardine
Contributing Editors

PATENT NUMBER:

6,191,483

ASSIGNEE:

Philips Electronics North America

INVENTORS:

Mike C. Loo

TITLE:

Package Structure for Low Cost and Ultra-Thin Chip-Scale Package

This patent describes the manufacture of a CSP that offers a more reliable way of mounting a flip-chip device to a printed wiring board than previous methods. This approach also results in a much thinner package overall.

Prior Art

Two examples of prior art were cited. The first example is a flip-chip device mounted on a conventional PWB. The typical laminate thickness at the time was 1.0 mm (40 mils). The large mismatch in TCE between the PWB and silicon IC puts the solder joints of the flip-chip under considerable stress, leading to premature failure.

Underfilling can be applied to give added support to the solder joints, but there can be problems with this approach, since underfilling may cause die cracking and delamination if the stress is large enough or frequent enough.

One solution is to use a ceramic substrate. Ceramic with a TCE of 7 ppm falls between the 17 ppm of the PWB and the 3 ppm of the silicon. When underfilled, this approach has been shown to be a very reliable method of packaging flip-chip devices.

The problem with this approach, however, is that a thick ceramic substrate must be used. Ceramics are relatively brittle materials. When alumina ceramic was used as the substrate, the thickness had to be at least 0.65 mm (25 mils) so that the substrate did not crack during processing.

The thick substrate resulted in a package that was too thick for most handheld applications, thus a better solution was required.

Ultra-thin chip-scale package

Composite Substrate

In this patent, the advantages of a ceramic substrate are maintained, but the substrate is made much thinner using a composite approach. The composite described in this patent is only 0.2 mm (8 mils) thick. To minimize or eliminate microcracking, both sides of the substrate are coated with thin organic layers.

Via holes are formed in the ceramic substrate and used to connect the pads and traces on one side of the substrate to traces and pads on the other. The substrate metallization is performed using conventional thick film screen printing.

After metallization, thin organic epoxy layers are applied to each side of the substrate. The organic layers have a thickness of 0.025-0.075 mm (1-3 mils) and can be applied by deposition or lamination. No information is provided as to the specific epoxy material used.

The polymer layers do not cover the flip-chip pads or the CSP solder pads. It appears that the polymer layers are photo-imageable and that the pads are opened after the layers are applied. If the layers are screen printed, this step would be unnecessary.

The organic layers have a TCE greater than that of the bare ceramic, but no specific values are given. Additionally, the TCE of the composite ceramic substrate is greater than the ceramic substrate itself.

The addition of the polymer layers adds from 2-6 mils to the substrate thickness, but prevents substrate cracking and gives better solder reliability.

Assembly is straightforward. The flip-chip device is bonded to the composite ceramic substrate and then underfilled. Solder balls are added to the bottom pads to complete the package.

International Interconnection Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection areas. Contact David Francis or Linda Jardine by e-mail at iii1@ix.netcom.com or by phone at 650.728.5270. [iii1.com]
 
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