By Dr. Thomas Tschan, ESEC S.A., Cham, Switzerland
From microprocessors to digital signal processors, from smart cards and watches to driver chips of LCDs, flip-chip technology is entering IC packaging's mainstream (Figure 1). Generally speaking, flip-chip is the mounting of a chip with its active side facing the substrate. The electrical interconnection between the chip and substrate can be established by either solder bumps, metallurgy bumps, conductive polymers, anisotropic conductive adhesives, compliant bumps or pressure contacts. Market Drivers The main delay in acceptance of flip-chip has been a cost issue, since flip-chip's overall packaging costs are not significantly lower than traditional packaging when superior electrical performance is not needed for the packaged device. Flip-chip technology cost drivers are the chip bumping, underfill and the manufacture of high-density substrates to support flip-chip's high I/O counts. Shrinking die size is an inherent challenge for flip-chip technology, because it requires a redesign of the substrate with every I/O layout change. Nevertheless, today's trend toward higher device clock speeds, smaller devices for mobile and portable applications-as well as higher I/O count-make flip-chip the technology of choice. The technology offers superior electrical performance due to the shorter electrical connections between the chip and substrate, which results in the smallest possible package size. The attachment of high I/O devices becomes very cost competitive in flip-chip, compared to conventional die and wire bonding technology, since thousands of I/Os can be connected in a single process step. Assembly Flow After IBM created the C4 interconnection method, many other flip-chip technologies were developed to fill the need for a wider range of applications. Of these technologies, two, defined mainly by their bumping materials, gold and solder, are at the forefront today. These mainstream processes are similar and consist of two main steps: flip-chip bonding followed by encapsulation or underfill. In flip-chip bonding, the bumped die is typically first picked from the wafer, then flipped. An upward-looking camera identifies the bumps (or any fiducials) on the die for accurate alignment to the bond pads on the substrate. The die is then placed on the substrate. Depending on the flip-chip bumping technology, the device is either heated and pressed at the time of its placement, or the whole device is reflowed (or cured) in a furnace after the die placement. During either of these steps, the electrical and mechanical interconnects are formed. Flip-chip bonders are usually chosen based on their alignment accuracy and throughput capacities. In the second main step, the chip is encapsulated (or underfilled) with epoxy between the chip and substrate, unless the underfill has already been deposited prior to the die placement (which is the case with the use of anisotropic conductive film or no-flow underfill). Curing the underfill completes the flip-chip process. The underfill protects the chip, but more importantly it significantly improves reliability by evenly distributing the mechanical load (caused by the TCE mismatch between substrate and die) evenly across the substrate. Figure 2 provides a snapshot of the vast range of technologies for each assembly step.
SOLDER BUMPING Bump Materials and Processes Several factors influence the choice of the solder bump composition (typically Pb/Sn), including manufacturability, bumping process capability and reliability. One key factor is the melting point of solder, which defines the maximum process temperature of the assembly elements. The melting temperature of each element in the entire assembly process-the temperature hierarchy-must be taken into account. Thus, in an ideal situation, and to preserve the integrity and mechanical stability of the flip-chip solder connection, the flip-chip-bonded device must be further processed at a temperature below its melting point. As with virtually all flip-chip processes, to ensure a low and stable contact resistance at the bump-bond pad interface, the aluminum bond pads must be re-metallized to eliminate non-conductive aluminum oxide.
This remetallization is the reason for depositing an underbump metallization (UBM). In addition, the UBM (Figure 3) must fulfill the following requirements:
Today's standard process steps for UBM (Figure 4) include a native oxide etch prior to sputtering thin layers, such as Cr-Cr: Cu-Cu-(Au); Ti-Ti:W(N)-Cu or Al-Ni: V-Cu, onto the entire wafer surface.
After the definition of a patterned photoresist, which leaves all the pads open, the bump is deposited either by evaporation (the preferable technology for high-lead solder) or electroplated. In lower-end and more cost-competitive products, which require less reliability, the solder bump material is stencil printed and stud bumped, or the finished solder spheres are directly deposited. After the deposition, a reflow process forms the solder bumps (Figures 4 and 5).
Applications The majority of current solder flip-chip processes are based on the binary tin-lead (Pb/Sn) system. To allow optimum solder flow requires the solder to be applied to chemically dissolved metal oxides. In addition, the flux has a second function: it serves as a tacky fluid holding the chip at the exact placement position prior to reflow. The reflow of tin-lead based solder bumps shows the beneficial side effect of self-alignment. This occurs when the wetting forces of the melting solder pull a misaligned chip into exact position with the substrate during the reflow process (alignment accuracy specified as better than 25% of the bond pad dimensions). For highest package reliability, however, a washing process is sometimes added following the reflow and prior to underfill to remove any flux residues. All high-end microprocessors are assembled today using tin-lead solder-based bump metallurgy. This process is the ideal application for flip-chip, as such components are characterized by a very high number of I/Os as well as a high clock frequency. The latest DSPs, high performance ASICs, as well as some memory chips, now employ flip-chip assembly with great success. NON-SOLDER BUMPING Solder-based flip-chip technology is well understood and results in the highest quality packages. Cost pressures, however, combined with a lower process temperature requirement for certain applications (for example LCDs), drive the development of non-solder-bump flip-chip technologies. Another benefit of processing at a lower temperature is the ability to utilize less costly substrates that cannot tolerate the higher temperatures needed for solder connections. Recent environmental laws, which will prohibit the use of lead in a few years, are expected to further increase the interest in these technologies. The variety of alternative bumping materials is also extensive; however, they can be placed in three main categories: electroless nickel/Au bumps, epoxy bumps and gold bumps. The bumping process ranges from electroplating and stud bumping for gold bumps to screen printing for the epoxy bumps. The advantage of both electroplating and screen printing is that they are batch processes, while the stud-bumping process is a serial process. Because the bump heighth of these alternative processes is smaller than with solder bumps, smaller bump pitches can be achieved, providing a major advantage. Stud bumping, for example, can be performed on the standard die used for conventional die and wire bonding; no rerouting of the I/Os on the chip is needed. Attach Process There are two main processes for connecting non-solder bumps with the substrate: thermocompression and adhesive-based attachments. With thermocompression, the connection is achieved by applying force and temperature, generating (in the case of a gold bump on a gold substrate pad) a metal-to-metal bond. With epoxy bumps, a cured conductive epoxy-based connection results. The adhesive-based attachment utilizes one of three basic adhesives: isotropic conductive adhesives, anisotropic conductive adhesives (or film) and non-conductive pastes. In the case of isotropic conductive adhesives, the gold bump is glued to the substrate with the adhesive as the conductive layer between bump and substrate pad. Anisotropic conductive adhesives (or films) hold the chip in place. The electrical contact is made at each of the bump sites, where the miniscule conductive spheres within the adhesive touch each other and thus become electrically conductive material (Figure 6).
With the third type of adhesive, non-conductive, the adhesive acts as an underfill while holding the bumps onto the substrates thus achieving the electrical connection through a pressure contact. Adhesive-based processes exhibit lower thermal processing stress than solder processes, possess excellent fine-pitch capability, do not require any cleaning from flux residues and do not contain any lead. However, the limitations of the adhesive bonding are that the connection exhibits lower mechanical strength. It also shows a higher electrical resistance than solder connections and is more difficult to rework. Since these processes do not have any self-alignment, higher placement accuracy is required of the equipment, which typically reduces the manufacturing throughput. Non-solder-based flip-chip technologies, such as gold compression or conductive adhesive, are more frequently used for Smart Cards, RFIDs, tags and watches. ACF (anisotropic conductive film) is the technology of choice for the direct attachment of driver chips onto LCDs. Trends and Outlook Almost four decades after the introduction of flip-chip technology in volume applications, there is a continuously expanding market addressing numerous applications, through the development of a huge range of materials and processes. In the next decade, market demand for mobile products and more functional integration will dramatically increase, further driving flip-chip-based assembly. In addition to the growing range of applications, today's mainstream flip-chip technologies face two key challenges: significant reduction of overall package manufacturing cost without negatively affecting reliability and a successful transition to lead-free solder processes. Flip-chip certainly promises to be an exciting and evolutionary assembly technology with explosive growth in the semiconductor world, and soon in the electro-optical industry.
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