Chip-Scale Package Testing.

Revolutionary thinking is required to address the complex test needs of csps.

By Paul Emmett, ChipPAC Inc., San Jose

Chip-scale packaging represents a unique challenge for the semiconductor test industry, which must adapt existing technology to accommodate this revolution-or develop new handling concepts and platforms to test CSPs.

To address the handling of this new packaging technology, the test facility, handler and test equipment vendors must think in what might be called the three Cs of chip-scale testing: Carriers, Contactors and Conveyance.

Each of these must be considered when deciding on a strategy for handling CSPs, when presenting them to the appropriate ATE platform for testing, and even when simply moving the product through the manufacturing process.

Figure 1. The MCT 7632 test handler

Carriers
The concept of carriers for chip-scale packages presents the first challenge to the test operation, and, as a result, to equipment vendors. Currently, the preferred final method for shipping CSPs appears to be in tape and reel media. This final packing of the product is well advanced, and equipment exists today for this purpose. The real challenge is in the handling of the packages during the test process. One must decide whether to handle these minute packages in their singulated form, in strips, panels or tape form on a frame.
Numerous approaches have been taken to meet the challenge of testing CSPs in the production test environment. The resulting methods have largely been adaptations of the classic, hard-tooled, JEDEC-outline compliant plastic tray, and the more universal approach of a waffle style mini-tray, which holds the parts in place with surface adhesion. Both of these approaches present unique challenges for meeting cost demands and product placement accuracy, especially when dealing with the automated device handling equipment available on the market.

Hard-tooled JEDEC-compliant trays might sound like an excellent idea from the test handler vendorÍs perspective, since the trays provide extremely well-controlled indices for product location within the confines of the tray itself. Developing such a tray also has short term advantages for the testing organization, since it allows for a simple solution to loading and unloading the chip-scale product using conventional pick and place handlers. The major concern to this approach, however, is cost.

The expense of hard tooling to manufacture plastic trays is sizeable. Moreover, there is no fixed standard for the overall chip-scale package dimensions, which are totally dependent on die size. Thus, it hardly makes sense to tool a new tray for every possible dimension of chip-scale package that might enter the marketplace!

If cost were no object, and the semiconductor manufacturer were willing to subsidize the expense of tooling a tray for every potential die and overall package dimension, there still would be a need to incorporate strict disciplines for the recycling of these carriers.

The alternative to the hard-tooled JEDEC-compliant tray is a carrier conceptually similar to the waffle pack, but one that allows the device to be held in a relatively secure position in the XY axis. This concept has already gained some industry acceptance in several volume production test operations dealing with memory-type devices and utilizing conventional pick and place handler technology.

Reusable Trays
For example, specially adapted, surface-adhesive type mini-trays have been fitted into reusable, hard-tooled input carrier frames constructed of metal or plastic to hold multiples of these smaller trays. The obvious advantage to this small, surface-tension type of carrier is reduced cost and the ability to recycle the carrier inside the factory, where it is reloaded with new product for testing.
The key questions are how many manufacturing cycles these carriers can accommodate and how capable of accurate package placement are they? Without some sophisticated enhancements to current pick-and-place handler equipment, it will be difficult-if not impossible-to "pre-stage" the products from this type of carrier into the test contactor location with enough accuracy to accommodate their challenging size.

The fact remains that even when a better solution for handling chip-scale packaging does emerge, sometime in the future, there will always be a need for a singulated device handling solution. The occasional need to retest product prior to final shipment, or for quality reasons, essentially mandates that the capability to test singulated product must be maintained for the foreseeable future.

Several handler manufacturers, notably MCT and Delta Design, have proven solutions to the handling of singulated chip-scale packages for parallel testing (See Figure 1).

Contactors
The second aspect of testing chip-scale packages is the electrical interface between the targeted test platform and the device.
When fine pitch, leaded packages were introduced to the market, the test industry struggled to develop sockets for every size and lead count. For years we struggled with "co-planarity", bent leads and multiple inspection steps to detect and correct the mechanical damages inflicted to the parts during singulated testing in conventional sockets.

The emergence of the chip-scale package presents no less a challenge. First, there is the issue of making a reliable and repeatable electrical connection to the device under test. Second, there is the matter of accomplishing such a connection on devices where ball pitch is sub-millimeter in span.

There are also constraints in the pitch and hole size which load-board manufacturers can produce to accommodate conventional through-hole socket applications. Coupled with this is the cost of developing mechanically sound, singulated package sockets in every dimension to handle non-standard CSP sizes.

Proposed Solutions
Many socket manufacturers have developed and proposed solutions to this challenge by employing impregnated materials or micro-pogo contacts in their socket solutions. The major issues here are initial cost, the number of useful test cycles in a production environment and reparability on the shop floor.

If we assume that all the above objections can be resolved, the issue then becomes one of how to design, fabricate and deliver a contactor mechanism, which will allow for multiple-point contacts per ball on the device. The contactor must also accommodate multi-site testing of 4, 8, 16, 32 units and above for memory-type device testing.

Resolving these issues requires a new and likely revolutionary change in the way we approach contactors. One promising approach has been developed by Micro Module Systems (MMS) of Cupertino, Calif., (Figure 2). MMS has developed a membrane type of contactor solution for the testing of multichip-module packaging substrates that should be adaptable to chip-scale packages.

The challenge in adapting this technology into the production environment has become one of how we handle the product inside the test handler equipment. Here is where we must logically break from the traditional concepts of singulated unit testing, and focus more on revolutionary concepts that will allow testing packaged devices in strips.

Conveyance
The last part of this challenge to the efficient testing of chip-scale packages is how to approach the matter of movement of the device, strip or tray inside the handler equipment and how to present it to the contactor assembly for testing.

The design and efficiency of any test handler which can pick up chip-scale packages in a singulated format, position them accurately for testing, sort the product into multiple output bins, and do this for many units in parallel, presents an incredible challenge.

We have already seen that there are ways to adapt existing pick-and-place handlers to handle the singulated form of these packages. But improving the efficiency of the test facility and reducing overall cost demands an entirely new approach to the handling of chip-scale packages (Figures 3 and 4).

Chip-scale packages are all manufactured starting with tape, or with some form of laminate materials. These are precisely fabricated to accommodate not only the individual die requirements, but also the assembly equipment, which must attach the die to the substrate, mark the device and attach the solder balls. Having the product already on this well-controlled substrate, it makes sense to test the product while it is still in the strip or panel format. In fact, this would eliminate many of the issues now raised with carriers.

The challenge, then, is to develop a radically new handler technology that can handle CSPs in the assembled strip form. The machine-input stage would accept assembled strips from magazines or reels, position them precisely with the contactor element and track the testing results electronically for follow-on processing. The product would then be singulated after testing. If this concept in strip handling can developed, it could take advantage of highly dense multi-site contactors like the MMS membrane design for parallel testing, as a means to reduce test cost.

Assuming a machine like this can be produced, the final part of the solution is to get load-board and test equipment manufacturers to develop interface and test programming solutions for highly parallel testing of the device types which will employ CSPs.

Conclusion
Given the present state of the packaging industry, it is likely that there remains a long way to go before we will reach the ultimate test solutions, ones that will efficiently and cost effectively handle and test chip-scale packages. The test industry is looking towards the equipment vendors to cast aside traditional thinking and implement radical and revolutionary new handling concepts. With this change in thinking, cost effectiveness in testing chip-scale packages will be achieved.

Mr. Emmett is Director of Test for ChipPAC (formerly the Assembly and Test Division of Hyundai Electronics of America). He can be reached at 408.232.8076, fax 408.232.8126 or by e-mail at pemmett@hea.com.