May - June 1999
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Dr. Tom DiStefano on Wafer-Level CSPs
An Expert Looks at the Issues™
What are the key benefits of processing CSPs at the wafer-level?Wafer-level processing moves IC packaging from the mechanical, one-at-a-time assembly line into batch processing, something like what integrated circuits did for the transistor five decades ago. Similarly, integration of the package onto the chip by wafer-level processing reduces costs, and—more importantly—enables added functionality, increased complexity and greater reliability. For example, incorporation of copper wiring layers in the wafer packaging is a very effective way to add high performance wiring into the IC.
What limitations does wafer-level processing place on CSPs?
Obviously, the size of the first-level package must be no larger than the size of the die. This limitation is offset, however, by several advantages wafer-level processing offers, particularly the ability to add wiring in the package layers to simplify the connection to the next level. One example is the use of power and ground redistribution in the package to obtain better noise isolation, as well as to reduce the I/O from several thousand to less than 1,000 on typical high-performance microprocessor chips.
How will wafer-level processing impact final CSP cost?
Wafer-level processing can be viewed as an extension of the trend toward producing CSPs in arrays of increasing size to achieve efficiency. Beginning with arrays of 30 CSPs, then to arrays of 100, and finally to full wafers at a time. A more significant factor is the reduction in cost of the IC itself due to savings in testing, inventory, shipping and logistics items which can be greater than the total cost of the package itself.
What differences are likely between wafer-level CSPs from different suppliers?
Many technological approaches are being developed. They generally fall into two categories: Layers added to the wafer sequentially or a package fabricated separately and joined to the wafer after it is complete and tested. The sequentially processed types are usually flip-chips with some sort of connection, either a solder ball, post, organic bump or spring. The parallel-processed type, on the other hand, allows for wiring layers that are fabricated separately and tested before joined to the wafer, enabling the addition of copper layers to the wafer with an acceptable yield and efficiency.
What are the equipment considerations?
Wafer-level packaging will drive a restructuring of the backend of the wafer fab to capitalize on the inherent efficiencies. Equipment needed to finish the packaging of the wafer is similar to equipment used in the front end of the fab. Some development of equipment may be necessary where unique fabrication processes are used. Moving burn-in and final electrical test into the fab will impact equipment as well. These requirements represent a significant opportunity for semiconductor equipment suppliers.
Will wafer-level processing mean the end of conventional IC assembly?
Not at all. Remember that to be a candidate IC, the finished package must be chip-size and the chip should be a high volume part. While specific applications, such as memory chips, are suitable for wafer-level packaging, the bulk of IC packaging is larger than chip size, and because of limitations in grid pitch and density they can't be supported by PWB substrates. As the field of chip-scale packaging evolves and high-density substrates enter the mass market, I anticipate that IC packaging will move toward wafer-level processes.
Isn't wafer-level packaging just a replay of wafer-scale integration?
Wafer-scale integration had the quite different and more ambitious objective of integrating a complete function onto a portion of a wafer by utilizing interconnect layers on the wafer to stitch together pretested and known-good functional chips. Wafer-level packaging simply fabricates the packages on chips in the wafer format.
How will wafer-level processing affect performance and reliability?
By adding high-performance copper wiring to the packaging layers, the designer has more options that he can use to increase chip performance. Certainly, power and ground distribution is best done on the packaged chip rather than in the substrate, as is the case with flip-chip. Beyond that, critical redistribution, intra-chip wiring and clock trees can be implemented in a low-resistance microstrip format for highest performance. Additionally, advanced signaling protocols that make use of wiring in the package are just beginning to be explored.
What factors are driving wafer-level packaging
Cost reduction is an obvious factor, beginning with the cost of the package and then extending to streamlining the backend of the fab. For example, final test can be done directly on the wafer, eliminating the need for wafer probe before packaging. Shortening the logistics pipeline can yield significant savings in shipping and in reducing the depreciation of inventory value in a rapidly changing market.
Perhaps more significant than cost savings in the long run is the additional capability for low-resistance copper wiring that wafer-level packaging enables. Heavy power and ground planes, along with critical networks, can be processed in the packaging layers on the chip to provide added performance and functionality. Power and ground distribution are increasingly important as the switching voltages fall below one volt while the total chip current increases. The alternative is to distribute power and ground in more expensive PWB substrates needed to match high pincount §ip-chips, where the power and ground contacts often outnumber signal I/O.
What triggered the explosion in wafer-level packaging? And why now?
The field of chip-scale packaging began looking to wafer-level production techniques several years ago in a drive to lower costs, particularly for memory chips which is where CSPs were first used in volume. By fabricating the package in a batch process instead of assembling them one bond at a time, the costs can be brought down a learning curve, much like IC fabrication. Wafer-level packaging was, in fact, enabled by the emergence of chip-scale packaging over the past several years.
Why is additional low resistance wiring on the chip important? Isn't that what double-damascene copper does?
The double-damascene process is used for copper wiring on-chip, at a significant cost in processing and in yield loss. Adding thick power and ground planes in the packaging layers is easier than in the damascene layers on-chip, where solid copper planes are difficult to fabricate. Wafer-level packaging offers an easier way for the designer to add copper layers which are required for high performance applications.
Will wafer-level packaging change the way ICs are designed?
Not initially, but as designers need more low-resistance wiring, they will begin to use this capability in their designs, particularly in power and ground distribution. As Prof. James Meindl, Georgia Tech, has pointed out, high-performance interconnect has become the bottleneck in chip design, where scaling down to finer geometries in conventional wiring leads to increased RC time-constant delays. Low-resistance copper wiring in the package layers offers the designer a low-cost solution for improving interconnect performance.