Media Kit
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On Line Reader Service
 Publisher's Letter
SEMICON West: What a Difference a Year Makes!

 Assembly Lines
STS Defies Conventional Onshore Model for IC Package Assembly Plant

 Electronic Trends
RF Packaging Poses New Challenges

 Standards
Standardization of Quad and Dual-Inline Leadframe-Based CSPs Is Accelerating

 Wafer-Level Watch
Stanford Seminar Program Gauges the Impact of WLP

 On Test
Strip Handling Promises Better Throughput

 Industry News
Company News
People in the News
Research & Development Spotlight
Letter to the Editor
Inspection, Test & Measurement
Packaging Foundries
Calendar of Events
Editorial Index

 Features
Special Report: Flip-Chip Packaging - A 32-Year-Old Infant Grows Up
Bumping Services Provider Directory

Cover Story: Steppers vs. Aligners - Two Technologies Race for the Finish Line in Wafer-Level Packaging

Stacked Chip-Scale Packages: They're Not Just for Cell Phones Anymore!

Known-Good Die for Stacked CSPs: It's Not Your Father's KGD Anymore!

Packaging Trends in Cellular Phone Applications

An Expert Looks at the Issues: Dr. Tadatomo Suga on Interconnection Technology

 Tutorial
Wafer Bumping: A Guide to Selecting the 'Correct' Process

 Technical Forum
A Semi-Additive Electroless Ni/Au Process Offers a Low-Cost Wafer-Bumping Method

The Effects of Pb Contamination on Lead-Free Sn/Ag/Cu/In Solder

 Tools & Technologies
ESEC's 3088iP Wire Bonder and more...

 Opinion
Wafer-Level Packaging Is the Next IC Revolution

 Patents
CSP Manufacturing Process Lowers Production Cost and Improves Yield

 Archives
2001
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2000
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July-Aug Sept-Oct Nov-Dec
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Current Issue
An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics
July 2001

Calendar of Events

Subject to space available, Chip Scale Review will list conferences of interest to the international chip-scale-electronics community without cost to the sponsor. We regret, however, that we are unable to list events sponsored by commercial organizations. Please fax or e-mail your listing at least two months prior to cover date to the editor at 209.824.2799 or chipscale@cs.com.

July

16-20

SEMICON West
16-18 San Francisco, Moscone Center
18-20 San Jose Convention Center
The Greatest (Equipment) Show on Earth
continues its annual, dual-venue presentation. Wafer processing equipment is in San Francisco, while assembly, packaging and test returns to San Jose. Save time and money by registering online.
SEMI [semi.org]
August

8-13

Fourth International Symposium
on Electronic Packaging Technology (ISEPT 2001)
Friendship Hotel, Beijing, China
IMAPS [imaps.org]

September

17-19

SEMICON Taiwan
Taipei World Trade Centre
This will be the sixth presentation of SEMICON Taiwan. The country's total semiconductor industry revenue is $8.4 billion yearlyÑexpected to reach $43 billion by 2005 and over $60 billion by 2010.
SEMI [semi.org]

30-October 4

SMTA International
Co-located with Assembly Tech Expo
Donald Stephens Convention Center, Chicago
SMTA [smta.org]
October

7-11

IMAPS 2001: The 34th International Symposium on Microelectronics
Baltimore, Md., Convention Center
The sponsor bills IMAPS 2001 as "The largest symposium related to microelectronics packaging in the world."
IMAPS [imaps.org]

16-17

SEMICON Southwest
Austin, Texas, Convention Center
Contact Terry Berke [tberke@semi.org]
SEMI [semi.org]

 
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