Stacked Chip-Scale Packages:
They’re Not Just for Cell Phones Anymore!
The density of silicon integration has outpaced the wiring capacity of printed wiring boards. As a result, system-level interconnect density is threatening to limit the added functionality represented by systems-on-a-chip, forcing designers into innovative solutions such as 3D packaging.
By Lee Smith and Ted Tessier, Amkor Technology Inc., Chandler, Ariz.
From an applications engineering perspective, the continuous pressure to reduce size, weight and cost, while increasing the functionality of portable products, has created a tremendous demand for innovative, cost-effective, minimalist IC packaging solutions.
This pressure is escalating across a broad range of applications from handheld communications and computing products to the recent explosion of digital imaging and MP3 audio products.
The integration of more features, functions and larger displays into these products has driven designers to pursue 3D (volumetric) density solutions to meet size, weight and cost-reduction roadmaps.
This article will provide the reader with an introduction to the stacked chip-scale package (S-CSP), the industry's first low-cost, high-volume 3D package.
The article will also explore the benefits that 3D packaging has brought to the mobile phone market and look at S-CSP adoption for new applications. The article will conclude with a roadmap for 3D packaging and examine why new applications are adopting 3D packages for density and cost benefits.
IC-PWB Density Gap Widens
The density gap between the semiconductor industry (which has remained on track with Moore's Law for doubling the number of transistors or functionality every 18 months) and the much slower-paced PWB industry has continued to widen.
This breach is placing tremendous pressure on the IC package to provide an effective space "transformer" between the submicron density of the IC industry and the much coarser sub-millimeter density of the PWB world.
One of the most effective ways for the IC packaging industry to keep pace with Moore's Law (without outpacing the PWB electronic platform's ability to wire higher levels of silicon integration), is through 3D packages that deliver volumetric density solutions through vertical stacking.
This class of packaging leverages advanced wafer thinning, along with die or extremely thin- package stacking technologies, to integrate multiple chips in a package that provides higher levels of silicon efficiency than achievable through conventional multichip or wafer-level packaging (WLP) technologies.
"Silicon efficiency" is defined as the ratio of the total silicon (Si) or die area(s) to the associated package area.1 A bare die or wafer-level package provides 100% Si efficiency because the package and die sizes are the same. S-CSP configurations are now in qualification or development that deliver up to 140% Si efficiency for a two-die S-CSP, and as high as 220% Si efficiency for a three-die S-CSP.
Figure 1. Waves of electronic packaging
Through the above 3D packaging innovations, a product designer can realize a 30 to 55% PWB area reduction vs. bare die or WLP solutions.
Stacked CSPs that integrate higher density devices, along with their associated higher I/O counts, may utilize die-to-die bonding and high-density interconnect substrates to handle the higher wiring densities at the package level.
As a result, the S-CSP enables both a reduction in the wiring density required in the PWB and a significant reduction in the PWB area required.(2)
Since the baseband section of a mobile phone (which includes the digital signal processor, microprocessor, memory and power management functions), contains the highest level of silicon integration and the associated highest level of printed wiring and SMT pad densities, this section has been the first area to adopt 3D packaging. This reduction in PWB wiring density and area can provide a significant cost reduction in product board fabrication.
In addition, the higher in-package interconnection density permits an increased solder joint pitch (second-level density), thereby increasing solder joint life without the need to add costly underfill or compliant materials.
The reduction in component density through integrating two or more devices within one package can provide additional savings in final assembly costs. These direct cost reductions, along with the indirect savings associated with fewer components to test, procure and rework, combine to deliver a total cost of ownership savings for 3D packaging.
Many applications that utilize either chip sets, high levels of silicon integration or large memory blocks may be able to achieve a significant total cost reduction through 3D packaging technologies.
The Fourth Wave of Innovation
Industry experts that evaluate the gaps between technology trends and technology roadmaps conclude that 3D packaging will be a key solution across a wide range of applications in electronic systems.
In one private study,(3) Prismark Partners considers 3D packaging to represent the fourth wave of packaging innovation.
Figure 1 provides Prismark's forecast for the waves of packaging innovation over a forty-year horizon.4 Prismark identifies 3D/stacked packaging as a strong fourth wave that could enjoy up to a 10% share of all IC packages by the year 2020.
To put this in perspective, in 2000 there were over 86.5 billion ICs produced worldwide. Some 94% of these were housed within a single package.
Prismark forecasts more than 127 billion ICs for 2005. By projecting at a conservative estimate of 8% unit growth rate through the year 2020, the 3D packaging share of 10% might total well over 40 billion components that employ stacking technologies.
Even if this forecast is off by a few percentage points, the market for 3D packaging is expected to be huge going forward.
It takes an early adopter to get things moving. If that early adopter is also a "killer application," growth skyrockets and provides economies of scale to speed adoption across other market segments.
Advances in stacked chip-scale packaging, driven by the tremendous demands and volumes of the mobile phone industry, are allowing 3D packaging to be suitable and cost-effective for an increasing range of new applications and die combinations.
The mobile phone market was a strong early adopter of CSPs, enabling the format to evolve rapidly and become more cost-effective in serving a wider range of applications and devices.
Industry forecasters agree strongly that the CSP currently has the highest rate of growth among all package types, due to the wide range of applications and devices for which its suited.
The mobile phone industry also has been a leader in seeing the benefits 3D packaging can provide for increasing functionality (including higher memory capacities) in shrinking handsets.
The initial 3D packages utilized by mobile phones attached the SRAM die on top of the FLASH die in industry standard stacked (S-CSP) configurations. As mobile phones continue to integrate more features and functions along with their associated increase in bandwidth and memory capacity, S-CSP adoption will continue to expand beyond the stacking of FLASH and SRAM devices.
Incursions will continue through the stacking of ASICs, mixed signal and processor devices, with DRAM and other high density memory devices.
The associated die sizes and bond patterns can require a unique range of die stack and side-by-side configurations to optimize the placement of multiple devices within the S-CSP family of products.
Some emerging applications are also evaluating the stacking of RF devices on top of logic with flip-chip bumps for the cost-effective integration of higher frequency devices, including global positioning systems, radio modules and Bluetooth components.
A recent industry forecast of S-CSP growth and penetration into the mobile phone market is provided by TechSearch International.
Figure 2. Cell phone/S-CSP market growth forecasts
Figure 2 represents TechSearch's forecasts for the cell phone and stacked CSP markets through the year 2004.5 Jan Vardaman, president of TechSearch explains, "When we originally forecasted growth for the stacked CSP six months ago, the cell phone industry was showing modest reductions from recent growth rates. Now, the high levels of excess inventory and softening handset demand have required a downgrading of our cell phone forecast for the next four years. However, new applications and broadening adoption of the stacked CSP indicate this forecast is in line or possibly conservative."
There have been a number of recent mobile phones that have used multichip FBGA packages (fine-pitch BGAs without die stacking) alone or in combination with S-CSPs.
To achieve further Si package integration for form factor and cost-reduction benefits, many new applications are combining three or more devices in a wide range of stacked and side-by-side die configurations.
Figure 3. Stacked package options showing die position designations
Figure 3 illustrates the wide range of die configurations available for integration within the stacked CSP platform. Contin-uous advances in wafer thinning, die stacking, die-to-die wirebonding and HDI substrates enable the S-CSP to be optimized for the specific requirements of the application or devices to be integrated.
By concentrating on the advancement of the above platform technologies and design rules, S-CSP configurations can be mass customized to deliver high performance and still meet declining cost requirements.