Four-Chip S-CSPs Figure 4 provides a SEM view of the die stacking, placement and die-to-die wirebonding associated with an advanced four-chip S-CSP that stacks two die on top of the large bottom die (with the fourth die to the side).
These four devices are integrated in a 15 x 15 x 1.4 mm 208 ball 0.8 mm pitch S-CSP for emerging wireless applications. A year ago this high level of Si integration and functionality may have been on a system-on-a-chip roadmap. Now advances in S-CSP technology allow semiconductor suppliers to look at design de-partitioning for cost and performance optimization. The design can be partitioned into multiple devices that utilize the fabrication process optimal for the analog, digital and memory functions vs complex mixed signal/mixed technology SoC fabrication. Package Roadmap The table summarizes some of the recent product announcements that utilize advanced, stacked CSP configurations (also referred to as multichip packages-MCP in Japan) to integrate leading-edge devices into cost-effective 3D packages. An emerging trend is to use triple-chip stacking to meet the higher storage and fast time-to-market requirements of new I-mode and emerging third-generation web-enabled handsets, while developing new, high-density memory chips. Memory stacking is still the dominant application for increased storage capacity, volatile and non-volatile combinations, as well as wider bus and word-width requirements. To deliver this range of 3D packages in reliable and cost-effective configurations (at very high volumes) demands additional advancements in the industry infrastructure.
Infrastructure Challenges S-CSP technologies offer several performance and form-factor advantages, which account for the rapid adoption of S-CSP technologies into portable products and the high rates of adoption expected for emerging/converging applications. There are, however, also some major considerations that must be anticipated to successfully deploy 3D-packaging technologies into ultra-high-volume applications. Since S-CSPs are essentially space-efficient MCMs, fully tested known-good die and burn-in capabilities at the wafer level are required to ensure that high yields at the package level are achieved. Cost and Quality Requirements Additionally, since full functionality test is often challenging with multichip packages, it is critical that the quality of the die going into the package be well- understood and that the substrate and assembly yields be near 100% to achieve cost and quality requirements. Initially, stacked CSPs were dependent on the relative die size of the devices to be stacked. Recent advances in wafer thinning and handling, film die attach stacking and wirebonding processes enable a wider range of configurations to accommodate most die size combinations, including same size die stacking. It is critical, however, that die shrinks be projected or carefully managed to avoid package changes, which can require requalification and lead to excess inventory and added costs. Since foundries tend to drive their own independent roadmap when it comes to die shrinks, sourcing from multiple foundries can be a challenge because relative die sizes may change substantially over time. To optimize cost and performance for System-in-Package (SiP) and multichip package integration (including stacking), a close collaboration between an OEM, IDM (integrated device manufacturer) and a full-service microelectronics manufacturer can provide tremendous advantages. This collaboration ensures that the application requirements are clearly understood, and that device design, and packaging design trade-offs can be made with a view to current and future device-shrink plans. Ideally, the different IC designs are optimized for stacking, both in terms of die size, stack up and die-to-die bonding. This task is critical in minimizing the S-CSP substrate interconnection density required. For applications where this consideration is taken into account up front, often a two-layer substrate with conventional design rules may be used. For other applications where die interconnection needs are not anticipated, or off-the-shelf die are combined, a substantially more expensive, four-layer build-up multilayer or micro-via (HDI) substrate may be required to accommodate the extensive in-package wiring, thereby driving up the overall packaging cost. If chip optimization is not feasible, implementing HDI at the package level through S-CSP or SiP technologies can still provide tremendous cost savings over HDI at the product level. In many portable product applications, the package height roadmap has been driven by single-die CSPs down to 1.4 mm maximum thickness for many applications today and to 1.2 mm in the near future. CSP Thickness Single-chip CSP thickness has set the standard for stacked die packaging in size- and weight-sensitive applications, including mobile phones. Tremendous pressure is on S-CSP providers to achieve 1.4 mm maximum package height for three-die stacks and 1.2 mm maximum for two-die stacks. Typical die thickness used in S-CSP applications is currently in the 150-175 µm thickness with sub-100 µm thickness emerging for extremely thin package- stacking applications. This drive for thickness reduction places pressure on backend, wafer and die-handling during the assembly process to ensure high yields. The degree of wirebonding complexity in S-CSPs is significantly greater than that of typical fine-pitch BGA designs. Wirebonding requirements impose constraints on a number of critical S-CSP design rules, including the relative die size of upper and lower die. The location of wirebonds in three dimensions along the length and loop heights of the wire connections must be considered to ensure the avoidance of shorting or cross talk between tiers of wirebonds. Additionally, the diameter and maximum length of the wirebond connections must also be considered, with respect to the extent of wire sweep, to ensure high assembly yields. The complexity of these various inter-related design constraints is significant and is very difficult to accomplish in a manual mode. Three-dimensional CAD design tools are being developed to allow thorough design for manufacturability assessments early in the design cycle.
Conclusion Three-dimensional packaging is experiencing tremendous levels of innovation and adoption in a wide range of new applications with more ahead, as Figure 5 shows. Mobile phone demands and stacked CSPs are driving advances and cost reductions that will provide compelling advantages for new applications that require new form factors, higher silicon integration or lower costs. Now that critical mass and the supporting infrastructure are maturing rapidly, S-CSP technologies may be the ideal integration solution for advanced packaging requirements. References 1. M. Kada, L. Smith, "Advancements in Stacked Chip-Scale Packaging (S-CSP) Provides System in a Package Functionality for Wireless and Handheld Applications," Proc. Pan Pacific Microelectronics Symposium 2000. 2. T. Swirbel, "Chip-Scale Package and Multichip Module Impact on Substrate Requirements for Portable Wireless Products," International Journal of Microcircuits and Electronic Packaging, V. 23, Nr. 3, Third Quarter 2000. 3. B. Swiggert, Prismark Partners, "Amkor Technology's Third Annual Customer Symposium," Prismark Partners, Santa Clara Marriott Hotel, November 1999. 4. Swiggert. 5. J. Vardaman, "BGA/CSP Development Update Service Q3 2000," Austin, Texas.
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