Current Issue An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics July 2001 Email the editor

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The integration of memory and RF is important for the cell phone industry. System-in-Package integration of different device technologies such as FLASH memory, SRAM, DRAM and ASICs, as well as diverse functions like base band, mixed signal and logic will be important.

SiP can utilize a mixed technology design that incorporates integrated passives and chip- and package-level designs into a single integrated whole. Figure 2 shows a conceptual SiP that incorporates embedded passives microvia laminate technology, single-level flip-chip CSP, stacked CSPs and direct-chip attach.

IMB Technology

A novel integrated module board (IMB) technology composed of integrating actives and passives into an organic laminate carrier using a non-solder attach method was recently reported.

Figure 3. Device cracking in stacked chips

Active components were embedded inside the carrier as chips-in-board (CIB). Interconnections and wiring were accomplished using a fully additive PWB process. Passives were fabricated above the chips.

Individual IMBs may be stacked to form three-dimensional packages. Inter-connections between the IMBs can be accomplished with plated-through-hole metallizations(18).

Reliability Issues

The functionality and portability demanded for mobile electronics requires extensive use of chip-scale packaging in their design. Portable electronics are much more subject to bend, torque and mechanical drops than other electronics used in office and business environments.

As a result, the traditional reliability thinking has undergone a paradigm shift. While most assemblies meet the thermal cycling reliability requirement, there is a concern that they may not meet that of mechanical reliability.

Many people have attempted to underfill the interspace between package and board with epoxy-based materials; however, underfilling CSP assemblies generally meets with mixed results19. The effect of underfills on thermal cycling reliability depends on the package construction type and board combination.

While leadless CSP reliability is increased with underfilling, there is little improvement with chip-on-flex and a lowering of reliability with TAB CSP.

However, you must be cautious about the choice and use of underfills, because an underfill that has a positive effect on thermal cycling reliability may have a negative impact on mechanical drop reliability, and vice versa.

Figure 4. Delamination and crack in underfill

Figure 5. Post-assembly cracks at the pad-joint interface with immersion silver finish

TCE Effects

The combined effects of TCE and modulus determine the performance. In addition, the adhesion of the underfill material to the various interfaces is important for effective stress relief. Filler settling in an underfill can be injurious to underfill performance.

In stacked-chip packages, you may encounter an even greater CTE mismatch between the laminate and the package. The failure mechanism may shift to chip damage instead of solder joint damage, especially when they are underfilled, as shown in Figure 3.

The total elimination of voids during underfilling is difficult, and excessive voids may reduce the effectiveness of the under-fills in stress relief. It is not uncommon to find cracks in the underfills during thermal cycling tests (as shown in Figure 4).

An important aspect in reliability evaluation is how the failure mechanism operates in the various stress environments. During thermal cycling, alternating compressive and tensile stresses are operative. Complex structural changes in solder joints, such as intermetallic growths, grain structure modifications (such as grain coarsening, elastic and plastic deformations due to creep), are operative.

Cracks initiate at the high-stress zones and propagate along the grain boundaries. In mechanical drop, the scenario can be different.

Failures occur along the intermetallic boundaries. Drop-dependent failures depend on the nature of the intermetallics that constitute the metallurgical bond. A copper-tin intermetallic bond may be stronger than the nickel-tin intermetallic bond in a eutectic solder joint. Too thick an intermetallic layer, however, is also deleterious for solder joint reliability.

The surface finish of the PWB also plays a significant role in the reliability of the assemblies. Common surface finishes are immersion gold over nickel and organic solder preservatives. The metallurgical bond in the former case is one of nickel-tin, while in the later case it is copper-tin.

Incidences of post-assembly hairline cracks using the immersion silver have been reported. (Figure 5 shows an example of a hairline crack.)

Conclusion

As the packaging industry migrates to increased miniaturization by employing higher levels of integration, we must recognize and address the reliability concerns at the product development stage.

Robust design, appropriate materials, optimized assembly and efficient accelerated test methods will ensure that reliable products are built.

References

1. T. Ishida, "A Vision of Electronics in the 21st Century," Proc.of the Fifth Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, Jan. 25-27, 2000, pp. 85-91.

2. R. Lu, R. Bo Tsai, V. Tu, et al., "A Study on Multi-Chip Package Technology-Dual Chip in TSOP II 54L Package," Proc. Pan Pacific Microelectronics Symposium, Jan. 25-27, 2000, pp. 241-246.

3. M. Gaynes, A. Emerick, P. Viswanadham, et al., High Density Integrated Circuit Packaging with Chip Stacking and Via Interconnections, U.S. Patent #6,002,177, December 1999.

4. S. Abu and J.J. Kim, Stack Package, S. Korea Patent #93-13050, Assignees: Samsung, LG Semicon, July 1993.

5. H. Jeon, Semiconductor Package, Korea Patent 93-28-278, December 1993

6. C. Burns, J. Roane, and C. Cady, Method of Assembling Ultra-High Density Modular Integrated Package, U.S. Patent 5475920, December 1995.

7. S. Oguchi, et al., Sealed Stacked Arrangements of Semiconductor Devices, U.S. Patent #5701 031, 1997.

8. S. Park, J.M. Kim, J.Y. Kim. et al., "Thermal and Electrical Performance of Stacked Chip Packages," Proc. Fifth Annual Pan Pacific Microelectronics Symposium, pp. 252-257.

9. P. Viswanadham, T. Chung, S. Dunford, "Chip-Scale Package Technology," Handbook of Area Array Technology, Kluwer Academic, 2001 (in press).

10. Y. Fukui, Y. Yano, Y. Matsune. et al., "Triple-Chip-Stacked CSP," Proc. 50th ECTC, Las Vegas, Nevada, May 21-24, 2000,

11. M. Kada and L. Smith, "Advancements in Stacked CSP Provides System-in-a-Package Functionality for Wireless and Handheld Applications," Proc. Fifth Annual Pan Pacific Microelectronics Symposium, pp. 246-251.

12. S. Cho, S. Park, M. Park, et al., "A Novel, Robust and Low-Cost Stacked Chip Package and its Thermal Performance," IEEE Trans. on Advanced Packaging, May 2000, pp. 257-265.

13. L. Higgins III, A. Schreiner, "Laser Structuring as an Enabling Technology for HDI and PSGA," Proc. Fifth Pan Pacific Microelectronics Symposium, pp. 23-32.

14. B. Houghton, "Solving the ELNIG Black Pad Problem," An ITRI Report, Round 2, Proc. International Summit on Pb-Free Solders, October 1999, p. S-04-3-1.

15. N. Biunno, "Root Cause Failure Mechanism for Solder Joint Integrity of Electroless Nickel/ Immersion Gold Surface Finishes," Proc. SMTA International 1999, Santa Clara, Calif., Sept 12-16, 1999, pp. 561-568.

16. D. Cullen, "New Generation of Metallic Solderability Preservatives: Immersion Silver Performance Results," Proc. SMTA International 1999, pp. 599-573.

17. J. Reed, "Risk Assessment of PCB Alternative Finishes," PC Fab, July 2000, pp. 26-42.

18. R. Tuominen and J. Kivilahti, "A Novel IMB Technology for Integrating Active and Passive Components," Proc. of the Adhesives in Electronics 2000 Conf., June 18-21, 2000, pp. 269-273.

19. R. Gaffarian and N. Kim, "Does Underfill Affect CSP Reliability?" Electronic Packaging & Production, July 2000, pp. 28-34.

Dr. Puligandla Viswanadham Dr. Viswanadham is a research manager at Nokia Mobile Phones. Prior to joining Nokia, he worked at Raytheon Systems Co., Texas Instruments and IBM. He has authored or co-authored more than 75 publications in the area of microelectonics packaging, and has authored a book on Failure Modes and Mechanisms in Electronic Packages published by Chapman and Hall. He also holds five patents and 15 invention disclosures. During 1974-78, Dr. Viswanadham was on the faculty of Ohio Dominican College, Columbus, Ohio, as an assistant professor. He earned his doctorate in chemistry from the University of Toledo, and an M.Sc. degree in chemistry from Saugor University, India. [viswam.puliglandla@nokia.com]