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On Line Reader Service
 Publisher's Letter
SEMICON West: What a Difference a Year Makes!

 Assembly Lines
STS Defies Conventional Onshore Model for IC Package Assembly Plant

 Electronic Trends
RF Packaging Poses New Challenges

 Standards
Standardization of Quad and Dual-Inline Leadframe-Based CSPs Is Accelerating

 Wafer-Level Watch
Stanford Seminar Program Gauges the Impact of WLP

 On Test
Strip Handling Promises Better Throughput

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Letter to the Editor
Inspection, Test & Measurement
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 Features
Special Report: Flip-Chip Packaging - A 32-Year-Old Infant Grows Up
Bumping Services Provider Directory

Cover Story: Steppers vs. Aligners - Two Technologies Race for the Finish Line in Wafer-Level Packaging

Stacked Chip-Scale Packages: They're Not Just for Cell Phones Anymore!

Known-Good Die for Stacked CSPs: It's Not Your Father's KGD Anymore!

Packaging Trends in Cellular Phone Applications

An Expert Looks at the Issues: Dr. Tadatomo Suga on Interconnection Technology

 Tutorial
Wafer Bumping: A Guide to Selecting the 'Correct' Process

 Technical Forum
A Semi-Additive Electroless Ni/Au Process Offers a Low-Cost Wafer-Bumping Method

The Effects of Pb Contamination on Lead-Free Sn/Ag/Cu/In Solder

 Tools & Technologies
ESEC's 3088iP Wire Bonder and more...

 Opinion
Wafer-Level Packaging Is the Next IC Revolution

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CSP Manufacturing Process Lowers Production Cost and Improves Yield

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Current Issue
An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics
July 2001
Letter to the Editor

Editor,

First, I'll introduce myself. I'm Bruce Gehman of SEMI in San Jose. After Murray Bullis retired in January, I became head of the SEMI International Standards Department.

You might imagine that I'm corresponding to rebut the negative-sounding comments about SEMI in your column (Assembly Lines) in the March 2001 issue. Sometime we might indeed chat about this, but that is not my purpose now. In your column you did speak about the SEMI standards program in terms that I interpret as being supportive. We appreciate this, and that is what motivates my contacting you.

One of the biggest problems in the SEMI standards program is revitalizing the assembly and packaging committees in the U.S. and Europe.

There is really, at bottom, only one problem: the identification of meaningful issues around which consensus "best practice" can be developed, and which have sufficient economic or technical impact to justify standards development activity. The backend seems to be so fragmented that there is little in the way of a clear path.

I'm an old (maybe "former" would be a more congenial term) packaging person myself, and I persist in the belief that SEMI standards can play a useful role in this area. I'm also convinced that if we are aggressive and resourceful, good standardization projects will start to materialize. (I read Chip Scale Review with the idea of staying informed and in the hope of identifying key industry issues.)

Dr. Bruce L. Gehman

Senior Director, International Standards, SEMI

Indeed, Chip Scale Review does support all meaningful standards programs. We will gladly assist Dr. Gehman in "revitalizing" the assembly and packaging committees. If you'd like to help, too, contact him at bgehman@semi.org-Editor

 
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