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Current Issue
An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics
July 2001

CSP Manufacturing Process Lowers Production Cost and Improves Yield
David Francis and Linda Jardine
Contributing Editors

PATENT NUMBER:

6,221,697

ASSIGNEE:

Advanced Semiconductor Engineering Inc.

INVENTORS:

Ching-Huei Su, Chih-Chang Yang, Shyh-Wei Wang and Chih-Sien Yeh

TITLE:

Chip-Scale Package and Manufacturing Method

This patent is a change from those presenting new and innovative ways of packaging devices, because it deals with a relatively simple improvement in a manufacturing process that lowers the cost of production and improves yield.

Prior Art

The general technology in this patent is the attachment of a substrate to a chip in a lead-on-chip (LOC) approach. The substrate type is not specified, but is probably a flex or TAB circuit.

The older, accepted method has been to attach the substrate to the front surface of the chip with an adhesive elastomer, shaped like the substrate with a central slot for accessing the bond pads on the chip. The substrate was part of a larger strip. (This elastomer is shown in the dotted line in A of the figure.)

There are two basic problems with the older approach. The first is that the process requires two separate encapsulation operations. The first encapsulation applies the resin in the slot area to protect the connecting bonds. This resin must then be cured before the strip can be turned over.

Then, the encapsulant is applied to the second side to seal the chip's perimeter. This second resin application must then be cured, which results in a two-step, two-cure process.

A second problem is that if the dispense needle or package is misaligned, or if the resin overflows the slot area, it can penetrate the holes used by the solder balls, which leads to a rejected package.

The patent presents a more-efficient CSP encapsulation process

This patent describes a process in which the encapsulation is performed in a single step and in a manner that prevents or eliminates resin overflow from contaminating the solder pads.

In hindsight, the solution is extremely simple. The elastomer pad is applied as two separate pads (as shown in B).

Suitable elastomer pads are made by both Ablestik and Hitachi Chemical under the trade name HS-205T.

In the original design, the one-piece pad features a slot in the center for making the connection to the bond pads. The only way to encapsulate this area was to apply the resin to the slot directly.

Encapsulation

In the improved process, the encapsulant is applied around the edges of the chip, and capillary action causes the resin to wick into the bond area, completing the sealing process in a single step (as shown in C). Eliminating additional filling and curing steps substantially increases throughput per hour while lowering manufacturing cost.

Since the resin fills the slot area via capillary action, it is difficult for the resin to overflow the slot and contaminate the solder pads, which results in improved assembly yield.

International Interconnection Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection areas. Contact David Francis or Linda Jardine by e-mail at iii1@ix.netcom.com or by phone at 650.728.5270. [iii1.com]

 
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