A Paris shopkeeper pulling up cobblestones in front of the Bastille would have no inkling of the awesome forces of change unleashed one summer evening in 1789. Events set in motion by the French revolution would topple ancient dynasties and leave an indelible imprint on the western world. The only certainty in a true revolution is change, but the far-reaching consequences are often difficult to foresee. Change is also manifest by the sweeping growth of wafer-level packaging, certainly a revolution in the making, and one with the potential to impact IC design and manufacturing at the most fundamental level. Wafer-level packaging today is moving forward rapidly, pulled by a behemoth-like, unstoppable engine. It is, simply, a revolution in the making, with the potential to impact IC design and manufacturing at a fundamental level. Recently, Prof. Richard Dasher of Stanford University hosted a seminar series, "The Impact of Wafer-Level Technologies on Advanced IC Design," to peer into the future and anticipate the impact of these new technologies. According to Prof. Dasher, "The wafer-level packages already out of the laboratories are just the tip of the iceberg. Combined with MEMS and optical technologies, wafer-level technologies offer a vast range of new IC options. He also noted that wafer-level may turn out to be a classic "disruptive" technology, incorporating improved cost effectiveness along with new enabling technical solutions. "Consequently, it's still difficult to predict exactly what devices and functions we'll see in the future. The series topics are only a glimpse into a few of the exciting possibilities." The Stanford series probed several dimensions of the emerging wafer-level technologies, including 3D. By stacking thin wafers to obtain 3D connected by through vias, chips can be wired for high performance without the use of cumbersome drivers. 'Natural Progression' In a sense, stacking wafers is a natural progression of stacked-chip packages that have proliferated over the past several years. The chip stack can be made thinner, and, perhaps more importantly, extended to higher performance. Part of the Stanford series was dedicated to MEMS, a rich source of techniques with much promise for wafer-level packaging.
Originally developed for sensors, MEMS processes are finding uses in packaging, where they enable new structures for inter-connecting chips and for added functionality. Although it's difficult to predict exactly how they will be used, MEMS technologies will find important applications in wafer-level packaging, including extensions to optical interconnect. One challenging aspect of IC design involves the fundamental limitations of conventional wiring layers. Power and ground distribution is becoming increasingly difficult because of decreased switching voltages and increasing currents. Using more solder balls to get power into the core causes an explosion of chip I/O. Power and ground dis-tribution in the package offers improved signal quality while reducing off-chip I/O. Additionally, RC delays in critical nets, such as clock trees and global buses, can be avoided by using impedance controlled wiring in the package. Although often overlooked, standards are a critical factor in the formation of any global industry. Recognizing this need, Jisso was formed in Japan to consider standards issues coherently across several levels from the IC, package and substrate through to assembly. Now open to companies outside Japan, Jisso is a forum for technological challenges in CSPs, wafer-level packaging, 3D structures, bare die and integrated passives, among others. Throughout all levels, a standard via grid converging for the near term at 0.5 mm, is viewed as essential for efficient interconnect. Fortunately, many of the eight-week seminar's presentations have been posted to a Stanford website. You will find them at http://fuji.stanford.edu/seminars/spring01.
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