July 1998
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Chip Scale and Flip Chip Made Easy: Progress of Worldwide Standards for CSPs
By Dieter Bergman, IPC, Northbrook, Illinois
Standards now being developed will help the infrastructure manufacture chip-scale packages and mount them - and bare die-on organic PC boards
The semiconductor industry has concentrated its products in several markets. These markets have enabled new chip designs to provide the processing speed and functionality needed for serving a particular market.
Figure 1. Component packaging requirements for different system types
Markets include such entities as electronic data processing, i.e., work stations, business transaction servers, personal computers and PDAs, electronic games and toys, stereos, cell phones and pagers, big switching systems and satellites. Each market has special needs, is looking for specific performance in particular environments and is making attempts to stay competitive among its counterparts throughout the world.
Market Drivers
Driving component packaging are thermal and electrical performance, real estate constraints and cost issues. The end markets typically dictate what's needed, with suppliers moving ever more quickly to beat the competition to market. Figure 1 shows an example of the component packaging requirements for various types of systems and markets.High-end microprocessors run at higher frequencies and require thermally and electrically enhanced packages. These enhancements are in the form of thermal vias, heat slugs, heat sinks, component towers and other ways in which to manage the thermal characterization. Electrical enhancements are usually provided through multilayer packages and in-package capacitance control features. Generally, hermetic ceramic packages are used for some of these applications.
Performance
For mid-range systems, performance is important, but so is cost. Therefore, thermally enhanced multilayer packages (plastic ball grid arrays or quad flatpacks) are possible candidates.For low-end and portable systems, cost and form factor are critical. Generally, surface mount packages, such as QFPs and thin small outline packages (TSOPs), and tape automated bonding (TAB) are used. The ideal component package is rarely obvious, however (Figure 2). Many feel that the robust assembly capability of the BGA, which has I/Os situated underneath the package body, provides greater system capability than the QFP, for example. The BGA is superior, it is thought, because pin counts in excess of 208 can stress the QFP's peripheral-lead arrangement. Yet both the QFP and BGA can be thermally enhanced, permitting their use in a greater range of applications.
Figure 2. Thermally-enhanced packages
Increasing functionality and speed requires more power, a higher number of bond pads on the die and more pins on the package. Fortunately, even with the increase in bonding sites, the I/O count is kept to a minimum by using decoupling capacitors in the package and on the die. In addition, by adding power and ground planes in the package, the number of I/Os can be further reduced. In enhanced plastic packages, I/O counts may be higher to avoid adding extra layers; thus, in-package capacitance is generally not feasible. For example, a microprocessor that has 168 I/Os in a ceramic package might require 196 I/Os in a plastic surface mount package. These conditions make the packaging characteristics very important to the assembler.
Flip Chip
During the 1960s, IBM and Delco practiced a totally non-packaged IC assembly methodology known as flip chip. It entailed providing solder "bumps" or connections on the component bonding site, with the package attached to the substrate in a face-down fashion.The logic family used at the time was standard transistor solid-logic technology. SLT transistors and diodes were glass-passivated at the wafer level to protect the aluminum wiring from the environment. The glass film eliminated the need for hermetic enclosures, because the transistors were sealed at the chip level.
The use of "known-good die," coupled with the determination that a die designed for wire bonding could be easily converted to an array format, has provided a new type of package that promises to provide the performance and thermal characteristics needed by the industry„but in a die-sized package. Figure 3 shows an example of one of the variations of chip-scale packages. Called a µBGA package, it has already been standardized by the Joint Electron Device Engineering Council (JEDEC), and many manufacturers (Hitachi, Intel) throughout the world have licensed this design.
The µBGA package is constructed via a flexible circuit, similar to TAB circuitry. The flex circuit is attached to the surface of an IC by means of a semiconductor grade elastometer. The flexible circuit structure forms the basic redistribution layer or interposer. Flexible ribbon-like bond leads of metal such as gold, gold-plated copper or gold-plated nickel, are bonded directly to the gold or aluminum pads of the IC. Thus, a chip can be used in a QFP, in which it is wire-bonded to a lead frame, or it can be repackaged in the smaller CSP configuration by having the interposer convert the peripheral bonding sites of the die to an array configuration.
Figure 3. µBGA Package
Figure 3 shows a single metal layer construction. However, µBGA packages can also be fabricated with two metal layers for power and ground distribution and controlled impedance designed for the highest level electrical performance. The elastometer, or compliant polymer layer, serves to decouple the differential expansion of the silicon from that of the interconnecting substrate. This compliant layer, together with the "S" shaped bond lead ribbon, effectively decouple the device from the strains of thermal expansion. The result: chip-size packages that are compliant in the x, y and z directions. In addition, this facilitates testing and assembly, while enhancing reliability.
The Need for ASICs
The most apparent advance for the semiconductor industry comes through the development of application-specific integrated circuits (ASICs). Integration in chip speed, both on and off the chip, have provided not only greater capability, but also greater challenges. Simply examing computer systems available during the past holiday season, one can quickly see that demands for greater performance have pushed systems from under 100 MHz into the 200-300 MHz range. Thus, the methodologies employed for companies in the data processing end of the market, the issue of greater integration and greater speed and more functional ICs for the specific application becomes paramount.
Figure 4. Cross-section of BGA packages
Figure 5. An example of the microvia structure
Advantages
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Minimum Size Characteristics
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To buffer increases in chip speed, new materials are being researched for wafer-level interconnect (as evidenced by the announcement from IBM and others to use copper wiring instead of aluminum). These advances may have implications at the chip-to-substrate interconnect level, too.
Moreover, what will be the packaging solution that meets not only electrical performance, but effective thermal management, and how will software systems model the circuitry? The package size is already being shrunk to meet the miniaturization requirements of hand-held products. Nevertheless, the most challenging issue of all is the cost of the solutions. This holds true not only for the degree of integration in the die, but in the package that supports the next level of interconnect.
Systemizing integrated circuits for a specific application has long been a way in which manufacturers have differentiated, their product from their competitors. By addressing the specific needs of a system, bØØ status: idle mainframe, the electronics designer can achieve greater performance without necessarily increasing semiconductor package size.
The arrangement of transistors, memory, and other logic functions on a single die provides system architecture that is functionally cost-effective, leading to the day when a total system in the application may be contained on a single chip. To achieve these goals, designers continue to ask for greater integration on each ASIC that they produce.
| Year of First Product Shipment (Year 1) | 1997 | 1999 | 2001 | 2003 | 2006 | |
| Feature Size (nano-meters) | 250 | 180 | 150 | 130 | 100 | |
| Logic Factors (M/cm2)(packed incl. SRAM) | 3.7 | 6.2 | 10 | 18 | 39 | |
| MPU chip size (mm2) | Year 1 | 300 | 340 | 385 | 430 | 520 |
| Year 3 (2nd die shrink) | 180 | 205 | 230 | 260 | 310 | |
| Package cost (cents per pin) | Hand-held | 0.70-1.40 | 0.63-1.26 | 0.52-1.14 | 0.53-1.03 | 0.44-0.89 |
| Cost-performance | 1.40-2.80 | 1.27-2.52 | 1.14-2.28 | 1.03-2.06 | 0.89-1.77 | |
| Number of package pins/balls | Hand-held | 100-256 | 117-300 | 137-352 | 161-413 | 205-524 |
| Cost-performance | 256-600 | 300-732 | 352-895 | 413-1093 | 524-1476 | |
| Power Dissipation (watts | Hand-held | 1.2 | 1.4 | 1.7 | 2 | 2.4 |
| Cost-performance | 28 | 48 | 61 | 75 | 96 | |
| Minimum logic Vdd (Volts) | 1.8-2.5 | 1.5-1.8 | 1.2-1.5 | 1.2-1.5 | 0.9-1.2 | |
| Across chip clock (High-performance) MHz | 600 | 960 | 1570 | 1770 | 2075 | |
| Across chip clock (Cost-performance) MHz | 350 | 530 | 730 | 930 | 1100 | |
| Chip-to-board clock (High-performance) MHz | 250 | 480 | 785 | 880 | 104 | |
Table 1, from the National Technology Roadmap for Semiconductors, shows the relationship between performance characteristics of packaged chips, and predicts feature size, power dissipation, cost expectations of the package, and performance of clock and chip rise time. This table is intended primarily to give a snapshot of the goals being set by the semiconductor industry.
Building Relationships
Since semiconductor manufacturers have historically driven the rest of the interconnect substrate advances, they have inherently managed their own futures. Still, in looking at ways to reduce package cost, that industry is more closely considering printed board materials and manufacturing capabilities. Attaching a lead frame using wire bonding has long been a technique used for making small outline ICs such as SOPs and QFPs.Nevertheless, the robustness of Bsary to move arrays into the mainstream, the semiconductor industry is exploring the use of organic substrates. Figure 4 shows two examples of BGAs with bare die attached to an organic substrate.
Since the semiconductor industry is predicting greater need for I/Os, arrays will likely become the package of choice. Still, there are some hurdles to overcome. Package size and weight reduction are important. The coefficient of thermal expansion mismatch must also be addressed. What may be the final factor is the cost per pin.
New Materials
IPC's Interconnection Technology Research Institute has been working to develop new materials that will sustain the temperature excursions needed by the bare die. In addition, the Institute has several projects in the area of microvia technology. Microvias are very small holes, 150 µm or less. They can be produced through chemical or plasma etching, and with lasers, as well. The holes are then metallized to provide the interconnections through the core material, as shown in Figure 5. Microvia technology uses standard organic substrates; the small holes can achieve the interconnection and redistribution from the periphery of the die to the array pattern.HDI Design
In 1991, IPC released IPC-STD-275, "Design Standard for Rigid Printed Boards and Printed Board Assemblies." After six years, it is apparent that design standards are needed for flexible and rigid-flex boards, PC card assemblies, multichip modules and HDI. Using IPC-D-275 and the international structure for standards developed by the IEC as models, the design standards were reinvented.The IEC model requirements apply to all types of boards and have been combined into a single document. Subsets of that "generic" standard have been created to define specific requirements. An IPC committee is responsible for each of the sections of design hierarchy. The newly-formed HDI Structures committee, with its three subcommittees on design, materials and performance, was assigned responsibility for HDI requirements.
Figure 6. Design standard hierarchy
Figure 6 shows the design standards relationship. The segmentations allow easy updating of any of the sectionals, and yet provide a complete library for those that need all aspects of design at their fingertips. The design standards that specifically address the needs of HDI designers are IPC-2225 and IPC-2226.
Not all information on HDI design belongs in a standard, of course. Consider also that there is a good deal of tutorial information that the industry needs to absorb. IPC-2315, Design Guide for High Density Interconnect Structures and Microvias will be the first of the HDI documents to be released. This guide is expected to lead the way for other documents on materials, component mounting and performance, and should be available by this June.
Material Requirements
Materials used for HDI structures are relatively different from those used to manufacture standard printed circuit boards. There is a similarity in the dielectric properties, yet the thin HDI materials are coordinated with the process used to produce microvias or small plated throughholes. Some materials are laminated to a core structure; others are deposited. If the method for microvia fabrication uses photosensitive techniques, then the dielectric will contain a photo-polymer. There are several major techniques for producing microvias: mechanical drilling, laser drilling, plasma etching, chemical etching, etc., and for each of these there is a best material, although some techniques can use a variety of the thin materials.Fabrication of HDI structures requires that these thin materials be deposited on a core. The core may be passive„like a sheet of aluminum„or an active part of the circuit, like a multilayer printed circuit board. In addition, the HDI redistribution layers are used for single chip or multichip component assembly as well as completed printed circuit board assembly structures. The electrical and physical properties requirements for the materials are slightly different. In some of the HDI structures, the core is manufactured first, then HDI layers are added to one or both sides, depending on the design's functional requirements.
Structure Selection
Material properties are an important part of the HDI structure selection process. The material determination starts with the design envelope, and the components that must fit within that envelope. Obviously, it is highly unlikely that electronics for a washing machine will ever need the miniaturization necessary for a mini-camcorder or cellular phone. Nevertheless, the performance issues must be understood in order to make the proper decisions as to when (or when not) to enter the world of HDI product development.
Figure 7. Material performance requirement hierarchy
The HDI materials subcommittee is working diligently on the requirements for the IPC-4104 to meet the expectation of users of these materials (Figure 7). The information is needed to either produce electronic components, where the I/Os of the die are redistributed from a peripheral pattern to an array pattern, or for a completely functional electronic assembly.
Cost Issues
As with almost everything, cost is the major hurdle. Users want faster microprocessors and ASICs that meet specific performance demands. Meanwhile, suppliers are stretching to meet integration requirements„the combination of memory and logic functions on a given chip„and to provide users with a package that is economical, can be easily interconnected and has a cost profile that meets the market's expectations.In fact, developing ICs has always been a competitive business. The big suppliers in the U.S., Europe and Asia compete globally, each trying to outdo the others in IC speed, performance and functionality. Time-to-market is critical. Those companies that reach the marketplace first tend to be the ones that obtain the necessary market share to recoup their investments.
Development costs can be significant; design teams are continually stressed to be productive as management attempts to keep the design team to some manageable number.
A design team developing semiconductors or ASICs usually consists of 25 design personnel or less. A group of this size incurs costs for labor and tools of approximately $150,000 per week. Since the time-to-market cycle seems to be a constant of about 50 weeks, one can easily see why the startup cost of a new microprocessor or a new chip set requires a premium payback in the first year and then is gradually reduced over time.
In the past, semiconductor firms devel-oped two types of teams. One team was for the global, customer-based market, with products intended to serve many markets and many product types. Microprocessors fall within this category.
The second team was dedicated to custom integrated circuits, ASICs. These devices were tailored to meet the demands of a particular customer or a particular product. Companies that were vertically integrated made great strides in product performance by integrating many functions within the semiconductor die, and thus provided cost-effective solutions to the cost-per-function issues related to a particular product.
One detriment, however, is the manner in which the semiconductor industry works with the next level of interconnection„the dreaded "design thrown over the wall" scenario.
The interconnect industry has been criticized for not keeping up with the levels of performance found in semiconductor dice. Some of this "catch-up" relates to the package itself; some relates to the manner in which the I/Os of the chip were designed, and probably the most important was the attitude of "i.0t's not my problem." These philosophies can no longer prevail, and industries must learn to work in closer harmony if they are to achieve the full potential that chip integration offers to the end-product user.
| NEMI | (National Electronics Manufacturing Initiative) |
|---|---|
| NTRS | (National Technology Roadmap for Semiconductors) |
| IPC | (National Technology Roadmap for Electronic Interconnections) |
| EDA | (Electronic Design Automation companies) |
How Will We Get There?
Many industries have developed technology "roadmaps" to identify where they are heading. The roadmaps, listed in Table 2, are particularly relevant to the characterization and use of semiconductors:NEMI's members are typically large OEMs (IBM, Delco, Motorola, etc.), that seek insight into future miniaturization, speed, power and performance requirements. These companies represent the leaders in technology. Many of the products they market are hand-held, small configuration products and other battery powered devices. The NEMI roadmap details challenges for the semiconductor and interconnection industries, whose products are ultimately combined into functional equipment.
The NTRS covers manufacturing capabilities and reduction of the size of the IC geometry (over time). It details the future speed, functionality and power requirements. Staying out in front of the user by offering greater capability than needed, semiconductor manufacturers hope to maintain growth rates and to continue expanding their markets.
Their strategy is to provide greater integration and greater speed while taking appropriate measures for power and frequency. Then the only worries left for the user are device cost and time-to-market. Those who follow trends in new equipment releases know the product cycle pattern: About every six months a product is launched that offers greater functionality and capability, usually at reduced cost and often in a small form factor. Miniaturization, in fact, is a key issue in many of the roadmaps.
The IPC National Technology Roadmap for Electronic Interconnec-tions merges the OEM needs outlined by NEMI. It takes into account the anticipated advances in semiconductor (NTRS) technology and walks the difficult line in predicting how the printed circuit board and assembly will fit in.
PC board manufacturers and assemblers work closely to forecast methodologies for developing an interconnecting structure that is both robust and performance-driven. Furthermore, assemblers are searching for a package that is easy to assemble, easy to maintain and easy to replace on the substrates. IPC's roadmap also establishes the foundation for future board-level research.
Last, but not least, is the technology roadmap of the Electronic Design Automation industry. In fact, EDA suppliers are in an even greater catch-up mode than the PC board industry. Driven by needs for semiconductor automation, most of the original EDA roadmap concerns focused on semiconductor requirements, including modeling, simulation and process identification.
There is no doubt that end-product applications are driven by microprocessors and custom logic devices. Nevertheless, the EDA roadmap now recognizes the need to closely match the IPC and NEMI roadmaps more closely, since EDA suppliers must provide tools not just for IC design flows but also for board design characterization.
Approaching the 0.1 µm Process
As the semiconductor industry approaches the 0.1 µm process for semiconductors, it must consider interconnect signal transfer, noise margin, power leakage and GHz signal speeds in digital designs. Printed circuit board designers presently work around the inadequacies of existing systems, yet can provide only marginal information to the PC board manufacturer. It's left to several follow-up discussions to pass on the complete product definition.Nevertheless, EDA companies hope to provide the automation tools that help the IC designer, the printed circuit board designer and the total simulation of a system that deals with the process characterizations impacting die performance.
The reason roadmaps are so popular is because they work. The SIA roadmap is often credited for pointing out the steps that industry needed to take to win back world market share. In 1993, the IPC roadmap identified a need for small via holes. Today there are 18 variations of methods to produce microvias. What all this has in common, of course, is a pro-active attempt to meet the challenges of interconnecting ICs.
Working Together
Roadmaps and industry challenges have proved to be unusual bedfellows. Never in the history of the electronics industry has there been a greater need for cooperation among those companies making semiconductors, companies providing the interconnection and assembly and companies that design and market the equipment to the end customer.In the electronics industry, OEMs send designs out to fabricators and assemblers, providing the information needed to manufacture parts, and thus underscoring a need for standardized design tools and documentation.
Standards are often identified by the manufacturer and user and, as such, cross industry lines. Accordingly, standards-writing organizations must follow their lead. In 1996, the industry worked together to develop "J-STD-012," "Implementation of Flip Chip and Chip-Scale Technology." This standard, supported by the Electronics Industries Association, IPC, JEDEC, MCNC, and Sematech, is really more of a roadmap, showing where the industry needs to be. However, it does identify standards that are necessary to achieve adequate communication among user and manufacturer. J-STD-012 identifies 20 standards that cross the boundaries of existing trade associations. Some examples of how semiconductor and interconnection companies are working together:
| J-STD-026 | Ü Semiconductor Design Standard for Flip-Chip Applications |
| J-STD-027 | Ü Mechanical Outline Standard for Flip Chip/Chip-Scale Configurations |
| J-STD-028 | Ü Performance Standard for Construction of Flip Chip/Chip-Scale Bumps |
| J-STD-029 | Ü Test Method for Flip-Chip or Chip Scale Products |
| J-STD-030 | Ü Qualification and Performance of Underfill Materials for Flip-Chip and Other Micro-Packages |
Conclusion
While technology roadmaps can help to bring industries closer together, we should understand that they identify challenges, but do not necessarily provide the solutions. It is the cooperation needed between different industries that will make those solutions a reality. To accomplish this, cooperation is needed on intellectual property rights sharing. Moreover, participants in the development of electronic equipment must work together for the total industry they serve.This paper was originally presented as the Chip Scale International ï98 keynote speech. It has been edited and is ©copyright 1998 Chip Scale Review, IPC and SMTA. All rights reserved.
Mr. Bergman is Technical Director of the Institute for Interconnecting and Packaging Electronic Circuits. A widely-known speaker on industry issues, he can be reached at dieter.bergman@ipc.org or by phone at 847.509.9700.