Attaching Die to Substrate: Rethinking a Traditional Assembly Process

The unique attributes of chip-scale packages are demanding the rethinking of a traditional assembly process by equipment suppliers.

Figure 1. CSPs, like the Tessera µBGA package which Intel has adopted as a flash memory option, are driving the development of new die attach methods.

The unique attributes of many chip-scale packages present a carrot and stick dilemma for assembly equipment suppliers. On the one hand, like any new and different package format, CSPs offer an expanded market for equipment. On the other, the needed equipment is not simple to build and can be quite expensive to design and develop.

Perhaps nowhere is the challenge for equipment makers more pronounced than in the attachment (or mounting) of the die to the package substrate. The demands that chip-scale packages place on the die attach process represent perhaps the greatest change in IC package assembly since the introduction of area array packaging, when the pinout gave way to the solder ball.

The roster of demands for CSP die attach equipment is short but comprehensive-with cost-effectiveness, automation, placement accuracy and high throughput topping the list.

Only a few years ago, you could easily categorize the equipment used to attach the die to the leadframe as a "die bonder" or "die attach system," but no longer.

Most CSPs will not be constructed with backside die attach. With the development of CSP processing where the leadframe has been eliminated, such as with Tessera's µBGA package, we now must now add a new category of equipment: "die mounting systems."

In the Tessera process, wafers are diced, then are picked-and-placed into waffle packs. These packs are loaded into an FCB-5300 bonder built by AnoTech. Manually-loaded trays of the elastomer substrate are also placed into the machine. The actual attachment is done offline, using the "nubbins" process developed by Dow Corning and Tessera.

Where current techniques can be used for affixing the die to the substrate, they will continue to be used, says David Francis, principal of International Interconnect Intelligence, Montara, Calif. "If the CSP uses a leadframe, a die will be attached using conventional silver-filled epoxy or a similar material."

In a growing number of applications, however, the die is being mounted with the active surface placed against an elastomer material, a PWB material, a leadframe or a flex circuit, Francis reports. In some cases, a simple adhesive layer is employed. In others, an adhesive-coated polyimide film is used - with a construction similar to lead-on-chip packages.

Much of the traditional die attach equipment is not suited to CSPs because it offers no provision for inverting the die before mounting. Since die are normally shipped face-up, they have to be inverted by machine or otherwise presented to the machine inverted.

"Inverting the die means that the front surface cannot be seen, and operators handling the die will be unable to determine the correct orientation of the carrier," Francis adds. "This mandates that die mounting systems will have to employ vision/pattern recognition systems to ensure proper orientation."

Because the die attachment process for the Tessera package is unique, and calls for a high degree of mounting accuracy, equipment suppliers are moving quickly to develop more cost-effective solutions to handle it, observes George Mello of chip giant Intel's flash memory operation in Folsom, Calif., (Figure 1).


Mello says that while not prohibitive from a package-cost standpoint, the die attach process for the µBGA format "will certainly be an area of focus for cost-reduction activity."


Figure 2. The ESEC Micron 2 die attach system is already in use at several chip-assembly plants.

Traditional die attach equipment makers, such as ESEC (Figure 2) and NEC-Nichiden (Figure 3), have moved quickly to supply machinery to handle chip-scale packages. Additionally, several non-traditional firms, such as MRSI, and companies known for other products (Anorad, for example), are also pursuing that area (Figure 4).

The specific package type is obviously the gating item where equipment is concerned. Pack-aging foundries, which now account for the major share of IC package assembly compared to the chip makers, have only recently started to move into CSP production.


Figure 3. The Nichiden lead-on-chip Model CPM-6100 features a pre-bake oven and can process both thermoplastic and thermosetting adhesives.

"The demands that chip-scale packages place on the die attach process represent perhaps the greatest change in the IC package assembly since the introduction of area array packaging, when the pinout gave way to the solder ball."

ASAT, a large packaging foundry headquartered in Hong Kong, counts decades of experience with die attach systems from many vendors. Edward G. Combs, ASAT's executive vice president of new product engineering, notes that the company offers fine pitch BGAs (near chip-scale) package assembly.

The newer die attach equipment, while closer to traditional die bonding, is suitable for FBGA assembly, Combs says. The FBGA packages are manufactured in a matrix format, so the die attach machinery used must be programmable to handle variations in indexing. Programmable write heads, rather than nozzle-type dispense heads, are employed to control the bondline thickness and voids.

The Integrated Packaging Assembly Corp., San Jose, is moving into CSP assembly following a recent license agreement with Tessera. Robert J. "Jim" Walker, IPAC's marketing director wants die attach equipment to be highly adaptable. It might need to dispense adhesive, place die and cure in place - all with one machine.

"The equipment may also need to offer vacuum capability for face-down die, where the underfill is employed as the die attach material," Walker adds. And since the substrate is not much larger than the die for CSPs, great accuracy is needed.

With the new demands being placed on equipment makers, it's obvious they are paying a great deal of attention to customer's current and future needs.

The trend is toward high throughput (1500-2000 UPH) with high accuracy (12 microns or better), with automatic handling of sawn wafers, according to Flynn Carson, assembly development process manager at Tessera, San Jose. "To achieve high throughput and accuracy, the trend is to minimize motion and perform 'realtime' alignment by looking at the die and substrate/tape fiducial in the same field of view," Carson adds.

NEC-Nichiden Machinery Ltd., a subsidiary of NEC, claims to be the largest supplier of die bonders to the Japanese semiconductor equipment market. Nichiden has developed CSP die attachment technology with a customer (presumably NEC) and with the NEC Package and Material Develop-ment Center, according to Hiroji Kunitomo, sales engineer-overseas marketing dept.

Known as the CSP High Accuracy Die Mounter, the machine is for flip mounting die onto flex-based packages in a face-down configuration. The machine heats, pressurizes, then accurately mounts the device onto the taped BGA. Leadframes are fed from the magazine, and the chips are picked up from a 300-mm wafer, then transferred to the mounting head.

Equipment flexibility has become more important than ever before, according to Bob Wise, marketing director, Kulicke & Soffa Industries, Willow Grove, Pa. "Semiconductor manufacturers may need the capability to pick die from many different forms and carriers, such as wafers, waffle packs and Gel-Paks®. The flexibility to process die with the full range of substrates may also be required," Wise adds.

The vast number of different CSP types (probably close to 100 are now in development), call for extensive modularity in equipment design, Wise says. "This modularity will enable users to select those features that are needed to optimize the desired parameters, such as yield, throughput, reliability, etc., while minimizing equipment cost."

To enlarge its share of the die attach/die mounter market, K&S recently began distributing the PPS multi-chip die bonder line in the U.S. and Asia. The bonders were developed by Datacon GmbH, an Austrian company.

The PPS bonders present the same footprint as many standard wire bonders, making the system unusually compact for a die attachment system. Depending on throughput needs, up to four pick-and-place modules can be connected to the machine and controlled through a single user interface.

Meanwhile, competitor ESEC SA in Cham, Switzerland, reportedly has several of its Micron 2 die attach systems running throughout the world for CSP production.

ESEC is seeing a multi-dimensional market, with some customers requesting equipment for flip-chip attach, others looking for µBGA package mounters and still others interested in more traditional die attach systems.

While many people are talking about flip chip, "significant technical challenges remain regarding the manufacture of a cost-effective package with adequate reliability," says Roland Heitman, general manager of ESEC's Integrated Component Placement Division. "Those flip-chip packages which have proven to be reliable are expensive, and when lower cost material sets are used, some reliability issues arise," he adds.

There is also a significant challenge to achieving low cost because the flip-chip infrastructure is still developing, making flip-chip compatible substrates and bumping, in particular, quite expensive, he says. While Heitman says thinks flip chip may be "the ultimate solution, I think it will still take time to get there."

Conventional die (and wire) bonding are still important market alternatives, ESEC believes, they are also a significant majority of the market, although they don't receive flip-chip's attention, Heitman observes.

ESEC is seeing a multi-dimensional market, with some customers requesting equipment for flip-chip attach, others looking for µBGA package mounters and still others interested in more traditional die attach systems.

"Higher die densities on BGA strips, combined with clever molding and dicing schemes make (conventional systems) an attractive alternative. Although flip chip is a more exciting technology, the cost effectiveness of more traditional methods will keep it around for use with CSPs for quite some time," he adds.

The challenge, reports Heitman, is optimizing low cost, reliability and footprint - because assembly room space is still an expensive part of each assembler's manufacturing overhead.

The packages that accomplish these goals most effectively will win. "Today, the Tessera package is one of the best." However, Heitman adds, "they recognize that significant effort must be made to continue to reduce the cost-per-pin or Tessera risks losing its leadership position."

Gary M. Catlin is vice president for equipment sales and service at Silicon Coast Associates, Austin, Texas, and a veteran of the semiconductor assembly and packaging industry. He says equipment makers appear to be working within the platforms used for other die attach requirements - such as LOC (lead-on-chip), TAB and flip chip to gain an early entry into CSP applications.


Figure 4. The AnoTech FCB-5400 flip-chip bonder can be used for die mounting a variety of CSPs, including the µBGA package. The machine was jointly developed by Anorad and ESC International.

LOC die bonders offer the recognition and geometric positioning needed to accurately place the die using either PR and geometric positioning with encoders or a combination of pre-location and in-situ position confirmation. These machines, adds Catlin, typically do not offer a dispense capability since LOC methods use adhesive "tape" pre-positioned on the leadframe. "Retrofit for dispense, especially in light of the small material quantity and accuracy required, may not be straightforward."

TAB equipment performs the same alignment, placement and bond functions for CSPs as they were designed to perform on tape-automated-bonded devices, however temperature/pressure requirements for CSPs are usually much lower, Catlin observes.

Flip-chip die bonders offer the highest flexibility to handle the different machine functions needed across the range of CSP devices, according to Catlin. "Consequently, modifications to this equipment 'platform' permit more precise tailoring of the process to fit the device."

Conclusion