Summary of Recent Activity in Japanese CSP Patent Applications

Linda Jardine & David Francis

CSP and near-CSP activity in Japan continues to grow, with virtually every major semiconductor/systems company entering the fray for smallest, lightest and most TCE-compliant package. In this issue, we'll examine five of the latest patent applications submitted in Japan.

Company: Hitachi Ltd.
Application Number: 9260533a
Title: semiconductor device and its mounting structure

Hitachi is a licensee of Tessera's mBGA technology. This patent application describes a key property of the elastomer layer that lies between the flex circuitry and the face of the IC (Figure 1). It is this layer that must absorb the temperature coefficient of linear expansion difference between an FR-4 type substrate and the silicon IC. The elastic modulus for this elastomeric resin must be between 50-750 Mpa to balance the strain on the solder bumps and the interconnect lead from the flex to the IC pad.

Company: Hitachi Ltd, hitachi vlsi engineering corp. and hitachi microcomputing systems ltd.
Application Number: 9260535a
Title: semiconductor integrated circuit device and its manufacture

This patent application is most likely an extension of 533A. In this application, a solder resist is applied to the surface of the flex to accurately locate the solder ball placement and to prevent the solder from moving down a conductive trace during reflow. A second difference addressed in this application is the use of an adhesive layer between the elastomeric layer and the IC.

The method employed here (Figure 2) makes sense if the elastomer and flex layers were assembled offline and then attached to the IC in a separate operation. One early Tessera process attached the flex circuit to the IC and then the elastomer was applied using an underfill-like technique. It would seem that there are a variety of ways in which this basic CSP package can be assembled.

Figure 1. An elastomer modulus is important for high reliability.

Figure 2. Elastomeric and flex layers are bonded together and then adhesively bonded to the IC.

Company: Sony Corp.
Application Number: 92107052a
Title: semiconductor device and manufacturing method

In this CSP application, the IC is attached to some type of PWB with adhesive and then bonded (Figure 3). Balls can be attached to the PWB or bumps may be formed by plating copper or other material. It is desirable to have the bumps extend above the level of the sealing resin. A predetermined amount of sealing resin is dispensed inside the seal cap. The IC assembly is then placed down into the seal resin causing it to flow around the IC, bonds and substrate. The cap can be organic or metal depending on the power level to be dissipated. It should be possible to bond the laminate substrate to the die while in wafer form. When attached, the die could be wire bonded to each substrate, as shown, while in wafer form. If the balls were attached after encapsulation, the flat, top surface of the substrate is available to pick up and handle the part without damaging the wire bonds.

For more advanced manufacturing, it should be possible to download data from wafer probe to the automatic wire bond equipment as to which die on the wafer are bad. This would eliminate the expense of wire bonding die known to be defective. While the substrate would be lost on each defective die, the relatively low unit cost of the substrate should be easily recaptured by being able to do much of the packaging while in wafer form.

The pads on the laminate should also be more rugged than those on the IC. Since the wire bonded assembly is very close to the final package format (except for the balls and encapsulation resin), it should be possible to do functional testing, at speed, of the packaged part while in wafer form.

Figure 3. This CSP is capped with predispensed seal resin.

Company: Nichia Chemical Industries Ltd.
Application Number: 9283803a
Title: chip led and manufacture thereof

This patent application (Figure 4) is included as a reminder to companies making passive components that while surface mount forced the first major decrease in component size, the movement to CSPs will force another major change in component size.

In this patent application, a chip-scale package is created for an LED. The LED is flip-chip bonded to a ceramic base that has wrap-around metallization. One way in which this can be accomplished is to form through-holes in the ceramic and then print conductive material in the holes as well as on the substrate's top and bottom. If the ceramic is cut in the center of the hole pattern, it creates an effective wrap-around metallization.

Flip bonding is used to mount the chip to eliminate the need for adding a backside wire bond.

Figure 4. LED CSP.

Company: Hitachi Cable
Application Number: 9092775a
Title: semiconductor device and

method of manufacturing it

In this chip-scale package (Figure 5), a PWB substrate is adhesively-bonded to an IC. Connections between the IC pads and the substrate are made using wire bonds from pads located in the center of the IC. The PWB is coined to form a step for wire bonding. The downset is sufficient to keep the wire below the top surface of the PWB.

The entire assembly is then injection molded to seal the device. The only portion of the PWB that is exposed is the portion to which the solder balls are attached. Either the substrate forms a seal to the mold die to prevent mold resin from filling the solder ball region or the die contains protrusions to accomplish the same task.

Figure 5. Molded CSP.

International Interconnection Intelligence is a market and technology research company specializing in the semiconductor pack-aging and interconnection area. Contact David Francis and Linda Jardine at 650.728.5270 or by e-mail at iii1@ix.netcom.com.