July 1998
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Joint Integrity of Chip-Scale Packages under Isothermal Aging
Thermal-mechanical wear of solder joints is the cause of failure for most CSP board assemblies, although failure at the board level can also be caused by internal package failure or by the solder ball/package interface in grid CSPs.By Dr. Reza Ghaffarian, JPL, California Institute of Technology, Pasadena, Calif.
The popularity of emerging miniaturized chip-scale packages (CSPs) is rapidly growing because of their benefits and smaller size, although they may be considered to be an interim solution. Many aspects of this technology, with the focus on assembly reliability characteristics, are being investigated by the JPL-led MicrotypeBGA consortium.
Three types of test vehicles were considered for evaluation, and, two configurations were built to optimize attachment processes. These test vehicles use numerous package types. To understand potential failure mechanisms of the packages, particularly solder ball attachment, the grid type packages were subjected to environmental exposure. Package I/Os ranged from 40 to nearly 300. The CSP packages were subjected to visual inspection and scanning electron microscopy (SEM) to characterize their joint quality, solder ball metallurgy and elemental compositions. They were then subjected to ball shear testing, with results compared to the plastic ball grid arrays.
After initial testing, these CSPs, along with BGAs, were subjected to isothermal aging at two different temperatures for two intervals. The exposed packages were then subjected to inspection, SEM, and shear testing, and the levels of damage were documented. This paper presents the CSP test results.
Miniaturization Trends
Projections regarding the use of throughhole and surface mount IC packages significantly differ, and the numbers depend on the source. One projection from BPA Limited in the United Kingdom is shown in Figure 1. Several trends are apparent:The dual-in-line package (DIP) had the largest decline in use, decreasing from 16 billion in 1996 to about 5 billion in ten years„equal to about a one billion reduction per year. In contrast, the use of surface-mountable packages, including PQFPs (plastic quad flat packs) are projected to increase in the next decade. The increase forecasted is from 7 to 18 billion within the first five years and will almost plateau with an increase of only two billion for another five years. Within ten years, the chip-on-board (COB ), not shown in the figure, is expected to increase from 5 billion to 13 billion.
Figure 1. Projection for Package Use 1996-2006. Source: Adapted from BPA, Surface Mount International 1997
The increase in the use of CSPs and flip-chip packages is the same, projected to reach 6 billion by 2006. In contrast, the increase in BGAs for the same ten years is expected to be minimal, reaching a total of only 1.5 billion. The projection for BGAs indicates that perhaps these packages are only an interim solution and are the stepping stone for the industryÍs wider acceptance of CSPs and flip-chip packages. CSPs meet the demands for higher density and lighter weight for miniaturized applications.
Why Chip-Scale Packages?
Emerging CSPs are competing with bare die assemblies. Many manufacturers now refer to CSPs as the package that is a miniaturized version of the previous generation. Two CSP concepts are shown in Figure 2. The concepts include: (1) packages with flex or a rigid interposer and (2) wafer-level molding and assembly redistribution.
Figure 2. Two chip-scale package concepts
Packaging accomplishes many purposes, including the following:
- Provides solder balls and leads that are compatible with PWB pad metallurgy for reflow assembly processes.
- Redistributes the tight pitch of the die to a pitch level that is within the norm of PWB fabrication. The small size of CSPs does not permit significant redistribution. Current cost-effective PWB fabrication limits full adoption of the technology, especially for high I/O counts.
- Protects the die from physical and alpha radiation damage and provides a vehicle for thermal dissipation.
- Eases die functionality testing.
Self-Alignment of Grid BGAs
CSPs can be categorized into grid arrays and leaded or not leaded using I/O expandability and manufacturing robustness, as shown in Figure 3. Key advantages/disadvantages of each category are also listed.Mini (fine-pitch) grid arrays can accommodate higher pin counts, and like BGAs, they have self alignment (centering) characteristics. For BGAs, the ease of package placement demands has been widely promoted as one of their advantages. This attribute has permitted a reduction in the number of solder joint defects to levels lower than conventional surface mount packages.
Many factors affect self alignment characteristics, but the main one is the molten solder surface tension that provides the pull force on the package toward the pad centers. The counter force is the weight of the package. For PBGAs, the pull forces induced from the melt of eutectic balls are larger than the forces from the partial molten joints in ceramic BGAs or solder paste melts in conventional packages. Hence, the result is better self alignment for PBGAs. The symmetry of BGA ball patterns further helps in allowing both X and Y as well as rotational placement offsets for BGAs.
Figure 3. Two chip-scale package categories
Grid CSPs
For grid CSPs, the molten surface tensions are much smaller than those found on BGAs, since the former have lower solder-ball volumes. This, coupled with the CSPÍs finer pitch, can degrade its self alignment performance, especially with heavy packages. Therefore, CSPs might require much tighter placement accuracy than 50-mil-pitch BGA packages.Grid CSPs show self alignment, but there is disagreement on the best offset limits.
- An offset of only 25% for a grid CSP with 46 I/Os was found acceptable. The acceptable offsets were 62% for PBGAs and 50% for CBGAs (Noreika, Surface Mount International, 1997).
- An offset of 80% was reported by another investigator (Partridge, Surface Mount International 1997).
- Only two bridges out of 16,100 solder joints were reported. These bridges were due to foreign materials with no defects found because of placement inaccuracy. The test was a qualitative determination in which three hundred CSPs with 46 I/Os were hand placed and reflowed with joint defects then characterized (Bauer, et al., Surface Mount International 1997).
- Only two solder joint shorts were detected out of 200 assembled CSP packages with 44 I/Os (Hunter, et al., CHIPCON '98).
Thermo-mechanical Failures
The thermo-mechanical wear (creep) of solder joints is the cause of failure for most CSP board assemblies. Failure at the board level can also be due to internal package failures or from the solder balls/package interface in grid CSPs.A non-uniform thermal expansion and/or contraction of different materials in the assembly induces mechanical stress on solder joints. To achieve the least damage to solder joints, thermal mismatch between the die and board should be minimized either by package optimization or by board materials that closely match the CTE of the package.
Only a few CSP packages have been designed to alleviate damage due to the thermal expansion of package/board mismatches. The floating pad technology (FPT) is another technique that was recently conceived with the aim of absorbing CTE mismatches at the pad level (Wojnarowski, ITAP '98). The literature data on assembly reliability of a CTE absorbed package, along with numerous other packages, was presented previously.(1,2)
Failure Shift
Assembly failure can be misinterpreted when there is a shift in failure mechanisms. For example, package internal TAB lead failures at heels were reported for the CTE-absorbed CSP„a fatigue failure mechanism shift from the solder joint to the internal package. An example of a theoretical cycles-to-failure projection with no consideration for failure shift is shown in Figure 4. A life of more than 7,000 cycles for a thermal cycle profile of -55ÁC to 125ÁC was projected. This is an order of magnitude larger than experimental cycles to failure of 1,000 to 1,500 cycles. The TAB failure just before assembly failure was detected at 1,000 cycles (Greathouse, CHIPCON '96).Ball/Package Interface Failure
For grid CSPs, the interface between package and solder balls is another potential failure site. This failure type was observed for PBGA packages after thermal cycling.
Figure 4. Fatigue failure projection based on the wrong failure mechanism assumption for a CTE-absorbed CSP.
For BGAs, cycles to failure and failure mechanisms under different environments were investigated under another program. Figure 5 (adapted from Ghaffarian and Kim, ECTC 1998), shows cumulative failure percentages versus increasing cycles for several plastic BGA assemblies. Wider distribution for two peripheral BGA packages is evidenced from this figure.
The exact causes of wider distributions are yet to be identified. Possible causes include: PWB materials (FR-4, polyimide), solder volume, and ball/package integrity. Ball/package integrity plays a role since failure analyses of cycled BGA assemblies indicated that failures occurred either at package or board interfaces. This means that solder joint cycling test results for packages from prototype or early production might not be representative of full production results. Wider distributions are also expected if processes are not optimized.
This investigation included BGAs as well as grid CSPs to determine if there were differences in ball/package interface integrity before and after isothermal exposure and if this correlated with cycles-to-failure test results. The isothermal temperatures were the maximum thermal cycling temperatures. The grid CSPs were from the list of leaded, leadless and CSPs. Their board assemblies are being evaluated by the JPL-led MicrotypeBGA consortium.
SEM Characterization
Representative SEM photomicrographs of CSP ball shapes and their interfaces are shown in Figure 6C. Photos for a TAB CSP from two suppliers are shown in 6A and 6B with a wafer version shown in C. Note differences in interfaces for the same package, which came from two suppliers, as well as different package categories. The TAB CSP-1 had a non-solder- mask-defined configuration, while the CSP-2 had a solder-mask-defined appearance. These differences might not be significant for this specific package since it is a CTE- absorbed package and assembley failure is not expected to be from the solder joint.
Figure 5. Wide distribution for two BGA package types.
Figure 6A. SEM photos of ball and package interface for wafer level
Figure 6B. SEM photo of ball and package interface for TAB CSP-1
Figure 6C. SEM photo of ball and package interface for TAB CSP-2
Shear Forces Before Isothermal Exposure
Figure 7 shows cumulative percentage versus shear forces for various packages. The median ranking (i-0.3/n+0.4) was used to calculate cumulative percentages. The 50 percentile shear forces, as well as their respective shear stresses, are shown in Table 1. It is interesting to note the significant difference in shear forces for different packages. Distributions for the same packages from different suppliers vary. The CSP-2 with a solder- mask-defined configuration has a tighter force distribution. SEMs of CSPs are shown in Figure 8. Generally, failures were ductile and were from the balls to package-pad interfaces. Two of the balls from the CSP-1 failed in the traces (right photo of 6A). The non-uniformity in interface failures for CSP-1 might be the reason for this packageÍs wider force distribution plots in Figure 7.
Figure 8. SEM photos of failure surface after shear tests for various CSPs
| Package Type |
I/O | Shear Diameter (mm) |
Shear Force (grm) at 50% |
Shear Stress (kgrm/mm2) |
Shear Stress 100 Hours at 100°C |
| TAB CSP-1 | 45 | 0.320 | 376 | 4.7 | 4.7 |
| TAB CSP-2 | 40 | 0.30 | 397 | 5.7 | N/A |
| Wafer CSP | 275 | 0.250 | 185 | 3.8 | 4.1 |
| Grid CSP | 176 | 0.170 | 172 | 7.6 | N/A |
Shear Forces After Isothermal Exposure
Results for those packages exposed to 100 hours at 100°C are also shown in Figure 7. The wafer-level package showed improvement after exposure. The most probable cause of this improvement is from microstructural changes which could have reduced the processing of residual stresses. This was not verified, however.Conclusions
- The allowable offset placement levels which result in grid CSP acceptable assembly are not well established. We postulated that a tighter placement control might be required for CSPs than is needed for BGAs.
- Failure shift from solder joint to package may occur more often for miniaturized CSP packages. A projection based on the wrong failure mode results in the wrong forecast cycles for failure.
- The MicrotypeBGA consortium was formed to system- atically address many of the CSP assembly reliability issues. The ball/package characterization performed was aimed at understanding other-than-board solder-joint sources of assembly failures.
- Ball shear forces were different for various CSPs. Shear force distributions for the same package type differ for two suppliers.
- Difference in shear forces depended on many variables including interface area, metallurgy, whether solder-mask defined or non-defined and failure mechanisms.
- A slight improvement in shear force or narrower distribu- tion was observed after packages exposure at 100°C for 100 hr. Improvement may be due to stress relaxation by annealing.
- Assembly handling may be an issue for those CSP packages with low resistance to shear force. Lower value in force did not translate to lower shear strengths (force/area).
References
- R. Ghaffarian, "Update on CSP Assembly Reliability and JPL-led MicrotypeBGA Consortium," The Third International Conference on Chip-Scale Packaging (CHIPCONÍ98), Sunnyvale, Calif., Feb. 12-13, 1998.
- Ibid. "A Review of Chip-Scale Package Assembly Reliability," The Second International Conference on Chip-scale Packaging (CHIPCON '97), Sunnyvale, Calif., Feb. 20-21, 1997.
Acknowledgments
The research described in this publication is being carried out by the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration.I would like to thank the MicrotypeBGA consortium team members and those who have been contributing to the progress of this program, especially J. Okuno and K. Evans for performing shear tests and SEM characterizations.
Dr. Ghaffarian brings nearly 20 years of experience in academia and industry to his current JPL post with an extensive background in mechanical engineering, materials and manufacturing engineering. He supports R&D activities at JPL for BGA, CSP packages and surface mount technology. He received the doctorate in engineering from the University of California at Los Angeles. Readers may contact him at 818.354.2059, fax 818.393.5245.
This paper was originally presented at Chip Scale International, Santa Clara, Calif., May 1998, and is, copyright 1998 by Chip Scale Review, IPC and SMTA. All rights reserved.