July 1998
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Results of a German CSP Project
A German consortium has developed several types of chip-scale packages, some with a pitch as small as 0.5 mm.By Jürgen Simon, Technical University of Berlin
Introduction
In 1995, a number of German companies and two technical universities formed a CSP consortium, Chip-Size Packaging in Micro System Technologies, to deal with the future requirements of chip-scale packaging. The consortium is funded by the German Federal Ministry for Education, Science, Research and Technology (BMBF) and is headed by the Technische Universität Berlin TU Berlin.The consortium began work in 1996, and the project is scheduled to continue for three years.
Project Targets
The project covers the whole range of chip-scale packaging, from the development of chip-scale/chip-size packages to the application of CSPs (Figure 1). The project includes the development of fine-pitch interposer technology (rigid and flex), high density interconnect PC boards and assembly technology. Results of the different consortium partners were compared through the use of a common test chip and test-board layout. Project participants are listed in Table 1.Project Participants
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The size of the common test die is 10 mm x 10 mm with 176 I/Os and a pitch of 200 µm. Different types of CSPs were built-up with this test chip. The grid array for these CSPs utilizes a pitch of 0.5 mm, although different array sizes were used (15 x 15 mm and 17 x 17 mm). The 15 x 15-mm array was designed to accommodate the loop length of the fan-in type rigid carrier CSP from MPD, Dresden.
In the case of the 17 x 17 mm array, the maximum number of lines between two adjacent balls is limited by two lines to facilitate interposer technology. The pin assignment of the different arrays and the test PC board were designed so that both CSPs could be used in the same mounting location, e.g. only one test board layout was required.
Figure 1. Project flowchart
Due to cost and yield considerations, test boards with only one metal layer and a minimum line width of 100 µm were used. Therefore not all I/0s can be measured individually. The test board allows two daisy-chained measurements and four-point measurement of the critical interconnects in the corners of either the interconnection between die and interposer or between interposer and board.
Development of Chip-Size Packages
CSPs for the program were developed by Siemens ZT, MPD and the Technical University of Berlin. Siemens ZT employed soldering for interconnecting the interposer, while MPD focused on wire bonding, which needs no die preparation. TU Berlin developed innovative wafer-level CSP processes.Siemens' Goals:
- The use of an existing TAB pilot line to realize flexible sub- carriers in different versions
- Feasibility studies on a build-up similar to TesseraÍs technology but with another pad preparation, lead material, outerlead bonding and bumping
- Preparation of samples for applications driven by miniaturization
Figure 2. Schematic of Siemens CSP, Version 1
The geometry of the first (face-down) version is shown in Figure 2. For the development of the flexible interposer, a number of problems had to be solved in connection with the intended process. A window opening for an excimer laser (248 nm wave length), with its carbon residues and residue removal, and an optimized solder resist pattern to improve planarity of the interposer, were only two of the challenges.
The test chip employs the TU Berlin-developed unit, which permits four-point and daisy-chained resistance measurements. The pads were prepared with electroless Ni and Au and the solder depot for flip-chip bonding was created using a transfer method. Selection of the alloy and the amount of solder for the different versions is still under investigation.
Connections between pads and interposer leads were experimentally done using a reflow process without any soldering tool. The result is shown in Figure 3. This area has to be protected by some type of resin encapsulation, but may be suited to simple gang bonding.
Resistance measurements and reliability tests are performed using a test board made from a sandwich material with a thick layer of FR-5.
MPD and TUB Projects
MPD focuses on wirebonding to interconnect a rigid carrier. Wirebonding is a well-established and widespread interconnection technology which requires no additional chip preparation. Chip-size wire bonding is "fan-in" and requires the interposer to be attached without contaminating the bond pads (Figure 4).Note that throughholes are not required for the interposer, allowing the cost to be reduced significantly. Figure 5 shows the bonded, common test chip compared to the wafer-level redistribution technology of the TU Berlin, which is strictly limited to fan-in (Figure 6). The redistribution technology utilizes an additional metallization on top of the die using thin„film technology and selective electroplating at the wafer-level. This metallization allows the rerouting of the peripheral bond pads to an array. Although the reliability of a simple wafer-level redistribution technology is limited due to the CTE mismatch between the silicon and the organic board, redistribution technology can be used for small dice cost-effectively (Figure 7A and 7B), without underfill.
Interposer Technology
Except for wafer-level technologies, a rigid or flex interposer is required for routing the terminals of the die to an array. Interposers with one metal layer are limited by the minimum linewidth that can be manufactured, since increasing the pin count requires an increasing number of lines to pass through the outer row of the grid array. Decreasing the pitch increases the problem.
Figure 3. Example of a CSP with a flexible interposer
Figure 4. Wirebonded CSP by MPO GmbH
Andus Elektronik developed rigid carriers for MPD's wirebonded CSP (Figure 8). To reduce the material cost in this particular CSP application required a single signal layer PC board. Andus can route three lines between the pads at a pitch of 0.5 mm using etching technology for a copper laminated base material like FR-4.
Laser Technology
LPKF Laser & Electronics GmbH investigated the combination of laser technology and electroless metallization as a solution to the production of very fine-line structures down to < 20 µm.
Figure 5. Wirebonded CSP with the common test chip
Figure 6. Wafer-level redistribution technology developed by the Technical University of Berlin
The basic idea of the process was to structure a special coating on the surface of the circuit carrier with a laser beam. This coating acts as a catalyst for electroless metallization where the circuit layout is built up. Laser structuring by mask projection is the only technique that enables the direct removal of material on an area of several mm2 with a single laser pulse. The homogenized beam of an excimer laser illuminates a part of the mask which is projected onto the PC board by a high-quality lens. Between consecutive laser pulses, the mask and workpiece are precisely displaced so that the single parts of the layout matched each other on the PC board.
 Figure 7A. Solder balls (300 µm) on Technical University of Berline's FC-BGA |  Figure 8. Andus Elektronic routed three lines between pads employing subtractive technology. |
 Figure 7B. A mounted wafer-level CSP on FR-4 material |  Figure 9. Fine-line capability of the laser process (0.35 mm pitch). |
This displacement enabled layouts of up to 50 mm x 50 mm to be structured with high resolution, employing a very few laser pulses. Layouts of 5 mm x 5 mm can be imaged by one single laser pulse so that movement of mask and target is not necessary. The short UV pulses, with high energy delivered by the laser, result in a well defined removal depth and a perfect structural acuity. The substrate material underneath is not damaged or modified. (The very fine-line circuit of Figure 9 shows a minimum line and space width of about 20 µm.)
Flex Technology
The Dresden University of Technology is developing a technology for fabricating CSPs with a flex carrier. The semi-additive technique is being employed for the interposer fabrication performed at wafer level. The use of semiconductor production equipment allows a higher resolution than does conventional PC board fabrication equipment. Polyimide foil, with a thickness of 50 mm, is used as a starting material. Both sides of the polyimide feature an adhesive-free, 5-µm copper metallization. The resist is deposited using a dipping method on the copper metallization, which is then exposed and developed. Nickel and gold are deposited by electroplating in the exposed structures. The conducting lines at the flexible interposer are fabricated using a differential etching process after the removal of the resist. This metallization system guarantees a reliable solder and wire bonding process for the conductor pattern.
Figure 10. Void-free (0.5-mm pitch) solder balls (Technical University of Berlin)
Figure 11. Design rules (0.5 mm pitch) for HDI PC board (Würth Elektronik)
The interposer is coated with a solder resist and the solder and wire pads are opened by photolithography. At this point, the interposer can be separated or the following processes can still be performed at the wafer level. The backside of the prepared interposer with the conductor pattern is bonded to the active side of the chip using liquid adhesives or adhesive foils.
Bumps with a pitch of 0.5 mm are then placed at the solder pads (Figure 10). A bump height of about 0.3 mm must be reached because of the wire bonds (compare Figures 4 and 5). This can be achieved by the solder printing combination with solder spheres. Mask printing is recommended for CSP fabrication at the wafer level.
High Density PC Boards
PC board technology is a key technology for the use of CSPs, since they require a high interconnect density. The well-known FR-4 technology can no longer fit the special CSP requirements due to interconnect density, extremely small area pitch and soldermask misregistration.Consortium member WÄrth Elektronik is developing high density PC boards for CSPs using DYCOstrate technology. WÄrth is concerned with microvias, microlines, via-in-pad (ViP) and optical registration systems. Using ViP technology, only two metal layers are needed for a CSP with a 20 x 20 mm grid array and a pitch of 0.5 mm. Via-in-Pad technology can also be used to reduce the requirements for soldermask registration if the signal lines can be completely routed in the bottom layer.
Design rules for a high density PC board are shown in Figure 11. The advantages of microvias are obvious: They can be placed in lands without generating problems for assembly or soldering, and packaging density, as well as wiring density, is clearly improved. Microvia technology is mandatory in area array packaging with a pitch smaller than 1.27 mm.
Cost Reduction
To reduce the cost for high density substrates, conventional FR-4 cores or complete FR-4 boards and RCF (resin-coated foil) were used by WÄrth. The RCF consists of an electro-deposited copper foil coated with B-staged epoxy resin (partially cured). This RCF is without glass reinforcement, enabling plasma and laser drilling to be used effectively for microvia formation.The process parameters for pressing and plating are nearly the same as for conventional boards. The resulting insulating layer typically has a thickness of about 35 µm. The resin can also be used to fill buried vias without additional processing. There are different thicknesses of resin coating available to reach the designed total thickness after pressing. The total thickness, however, is dependent on the layout and thickness of the copper as well as of the number and diameter of the buried vias.
The RCF has additional advantages including very good peel strength values of the copper and improved etching of fine lines and spaces because of very low profile copper. The low dielectric constant leads to improved impedance control and higher operating speeds. There are different resins available for high heat resistance.
Figure 12. The RCF is available in volume and is a comparatively low-priced material. There is no difference in assembly or soldering for the user, but testing of the bare board or the assembled PC board is sometimes a problem since probe needles can easily pierce the thin top layer.
Evaluation of CSP Assembly Technology
BUS Elektronik is concerned with the evaluation of assembly technologies for CSPs with a pitch as low as 0.5 mm within a conventional assembly line using solder paste printing or alternatively SIPAD technology. SIPAD technology uses planarized solid solder depots. With SIPAD technology, the solderpaste is printed, reflowed and planarized before assembly so that no solder printing is required during assembly.The most critical step is the solder deposition due to the fine pitch. The adhesion of the solder paste in the stencil is greater compared to elongated openings used for SMD components. As the amount of solder paste is reduced, differences during the printing process become more pronounced. If the solder printing can be controlled, subsequent pick and place and soldering is relatively noncritical.
Applications
Originally, an external CSP package with a common test die for qualification was to be used. Because the consortium felt the qualified version might not be available when needed, it decided to use a commercial flash memory IC in a CSP when the first CSPs became available on the marketplace. The selection of the flash memory enabled the consortium to learn commercial CSP assembly, essential for a company like BUS Elektronik. To demonstrate the advantages of CSPs, a memory module designed by D Engineering (Figure 12) was chosen.Summary
The consortium has developed different types of CSPs and their qualification is still in progress. The wire-bonded CSP is applicable to low volume because of inexpensive tooling costs. Small, wafer-level CSPs are being qualified by an external customer.An assembly technology for CSPs, with a pitch down to 0.5 mm, has been established and does not seem to present any significant problems. The most important issue concerning the acceptance of CSPs will be the availability of an appropriate PC board technology, such as microvias, at an acceptable cost.
Mr. Simon holds a diplom degree in physics from the University of Bielefeld, Germany. He has over 10 years experience in electronic packaging, specializing in TAB, flip chip and chip-scale packaging. He is currently in charge of the Micro Packaging Strategies Group at the Fraunhofer Institute of Microintegration and Reliability in Berlin. Additionally, he is responsible at the Tu Berlin for the German CSP consortium and for wafer-level CSP development within ESCHETA, the European ESPRIT project. Contact Mr. Simon at (49) 30 314-72 873, fax (49) 30 314 72 835 or by e-mail at simo1270@mailszrz.zrz.tu-berlin.de.
This is a revised and updated version of a paper presented at CHIPCON '98, sponsored by the Semiconductor Technology Center Inc. (SemiTech), Neffs, Pa. ©Copyright 1998 by SemiTech and used with permission. All rights researved.