July 1998
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Singulating Chip-Scale Packages
By Vern Solberg, Tessera Inc., San Jose, Calif.
Vern Solberg
Chip-size and chip-scale BGA devices are moving into the mainstream for portable and hand-held electronic product applications. These products require a minimal package size, and many of the companies targeting commercial markets are expected to consume everything the IC supplier can produce.
The first chip-size devices introduced to the market, in what the industry considers a volume production status, are flash memories. Several million devices are being produced each month and the demand is still growing. Materials used for CSPs may include plastic/epoxy laminate, ceramic or flexible polyimide films with the device sites uniformly spaced in a close matrix for efficient material utilization and handling.
The majority of these miniature BGA packages, which use flex-film material, are processed in a multiple array format and mounted on carrier frames for standard magazine-to-magazine handling.
The base interposer material can be furnished as a panel or in a narrow strip format typical of that shown in Figure 1, that can be easily transferred from one machine operation to another with little or no human intervention. This segment of the industry is growing very fast and numerous packaging methods are being introduced by companies from around the world. To maintain some physical continuity for these CSP device innovations, the IC packaging industry is moving quickly to develop standards and guidelines that will maintain a level of package uniformity.
Standards
The industry has already initiated standards in the form of a "registered outline" for chip-scale packages. The document defines a thin, fine-pitch BGA (0.50 mm array contact pitch) and has been released as JEDEC MO-195.*MO-195 specifies the mechanical features for 18 uniform, square device outlines but does not address the method or even the materials used in manufacturing. Although JEDEC and the Electronic Industries Association of Japan (EIAJ) have only approved one family of square package outlines at this writing, both organizations are working to expand the standards for several variations of the miniature packages.
The variations will allow optional profile heights and different pitch alternatives. Although a common ball diameter of 0.30 mm is preferred by a majority of the socket manufacturers surveyed by JEDEC, larger ball diameters may be considered for wider contact pitch variations.
In regard to the existing JEDEC document, profile tolerances established for these devices are very specific. Although reasonable latitude has been allowed to accommodate manufacturing variables, precise and uniform device singulation has proven to be challenging.
Figure 1. Flexible polymide film is bonded to a rigid carrier frame for efficient transfer from one machine process to another.
Profile Tolerance
The profile and contact features of the thin, fine-pitch BGA is referenced from a primary datum plane at the outside edge surface of the package. Although the size of the device is defined as a "basic" dimension without a fixed high and low limit, the profile tolerance at each edge surface has a deviation limit of 0.10 mm (4 mils).This profile control will allow the device outline to extend from the basic outline (for example 15.0 mm) by a maximum of 0.20 mm total (or 15.20 mm). The profile tolerance may reduce the overall package outline by the same factor, as well. However, what is most significant when singulating array type devices is the uniformity of the contact matrix in relation to the package outline.
The contact matrix must remain symmetrical to the package outline and the rows and columns should, of course, be parallel to the package edges as well. The MO-195 document specifies a tolerance of form and position of 0.15 mm (6 mils) for the ball contact. This tolerance is referenced from the ball center location to the edge datum established on the package outline.
Figure 2. This close-up view of two mBGA devices shows little difference between cutting methods. The device on the left was die cut, while the unit on the right was sawn.
Singulation Techniques
Several methods of singulation have been developed and most have proved they can hold these somewhat precise dimensional restraints without reservation. Most of the techniques use some form of mechanical system or mechanism to perform the singulation process. Some methods require dedicated "hard" tooling while others use numerically controlled machine technology and require only the development of a software program ("soft" tooling). Chip packaging foundries are already meeting the tolerance limits defined by MO-195 with a wide variety of methods.Singulation Methods
- Die punch (single or gang)
- Sawing (standard wafer saw process)
- Rotary knife (resembles a pizza cutter)
- Thermal-sonic knife
- Water jet (program driven)
- Laser (several variations available)
- Water/laser (water cools material after cut)
Not all of these methods will provide a satisfactory singulation profile for each of the base materials noted above, and die punching is limited to plastic epoxy laminates or flex-film material utilizing a dedicated fixture. The fixtures for this process are developed for a specific device outline and matrix configuration.
Dependent to a degree on the singulation technique, CSP devices constructed with compliant materials typical of Tessera's µBGA® and FmBGA» packages may exhibit a slight variation. The two edge-surface conditions compared in Figure 2, (one using a sawing process and the other die cut) vary slightly, but the finished device outline remains well within the established tolerance limits.
Materials
Because of the diverse physical characteristics of materials adapted for chip-scale applications, not all methods of singulation will furnish satisfactory results; indeed, ceramic base materials will be successful with only a limited number of the methods listed.Each of the methods noted, however, has a relatively comparable opportunity to achieve the requirements for accuracy for laminate and flex-film based CSPs and some companies may use multiple methods for singulation.
Higher volume manufacturers of a mature product, for example, will find that dedicated hard tooling is an ideal solution. Products being developed with a lower volume requirement, or manufacturers with a higher mix of package outlines, may consider a programmable system for separating the devices from the matrix.
*JEDEC is the acronym for the Joint Electron Device Engineering Council, a division of the Electronics Industry Association supported by member companies that manufacture IC devices, materials or supply services or other related products to that segment of the industry. For information regarding membership in the organization, or to obtain a copy of a JEDEC document, including MO-195, please contact the JEDEC office in Arlington, Virginia at 703.907.7560.
To contribute or to comment, please contact Chip Scale Review or Vern Solberg at Tessera by e-mail to vern@tessera.com or phone 408.383.3614.