Standardization Is More Than Just Package Specifications

In this column's discussions to date, I have concentrated on the standardization of chip-scale packages themselves.

A mature industry, however, needs standards of many more kinds to ensure successful usage of any new package. I would now like to outline some of the other standards activities which will have to be completed for CSPs to reach the mainstream acceptance that is anticipated. These activities will be discussed in detail in later columns.

Task Group

In addition to package outlines, the JEDEC JC-11 committee has established a task group to develop the basic design rules for shipping trays for fine-pitch BGAs. JEDEC has published design rules for standard trays in Section 10 of JESD 95-1. However, the size and weight of the FBGAs are so small that tray designs with the current nesting features may not hold the packages firmly enough during handling.

Some tray suppliers and users have observed that the packages may flip out of the tray pockets when they are jostled, during electrical test, for example

The task group has brought together tray manufacturers, package suppliers and end users to define an appropriate set of design rules for FBGA trays. A draft of the new document is being circulated for comments as a JC-11 survey ballot in the current quarter.

FBGA ball patterns for many device types are also subject to standardization, which is especially true for memory devices.

The JC-42 committee is responsible for this activity, and a number of proposals for DRAMs, SRAMs and flash memory are in process in the respective point committees in JC-42. Ultimately, these ball patterns and accompanying device pinout specifications will be published in JESD-21.

The definitions of ball patterns and the dimensional specifications developed by JC-11 form the basis for PC board layout rules. The IPC, which is responsible for standards relating to the PC board industry, has recently completed a draft of layout design rules for BGAs with pitches >1.00 mm; this draft is now circulating to the IPC membership for approval, and work has begun to define the layout rules for FBGA packages with finer pitches than 1.00 mm. When completed, these layout rules will be included in IPC standard SM-782.

Reliability is not usually seen as a matter which is subject to much standardization, since requirements vary widely, depending on the end-use. The product manufacturer defines the ultimate requirement-product lifetime-which may even differ over a range of similar products.

However, establishment of standard test methods and standard methodologies for data analysis is critical to the component supplier. These suppliers are unable to replicate exactly all of the use environments that any given component may experience and can use only a very limited number of test methods to provide the necessary data to customers.

Component Qualification

As packages have become increasingly smaller (and certainly since the advent of TSOPs), the well-established standard methods for component qualification have become less useful in establishing the suitability of the package to the given application.

The thermo-mechanical state of a packaged device may be very different after it has been assembled to a PC board, and even the assembly process itself may have contributed to thisdifference.

The evaluation of second-level, or board-level, assembly reliability has become a significant internal activity of most CSP suppliers. Of course, the question of how to do this evaluation quickly arises. At least two industry groups have been addressing the issues: JEDEC and the High Density Packaging Users Group.

HDPUG has developed an Application Specific Qualification Method specification that incorporates board-level testing, which has been circulated for comments in the JEDEC JC-13 committee.

The document is being proposed as a new JEDEC standard. Within JEDEC, an Interconnect Reliability Task Group has been developing a specification to define the test conditions for board-level temperature cycling, analogous to the standard test methods in JESD-22. This document is also being presented to JC-13 for approval as a new JEDEC standard.

Mr. Hayward is a senior member of technical staff in the Manufacturing Services Group at Advanced Micro Devices (AMD), Sunnyvale, Calif. He has been the AMD member of the JEDEC JC-11 Committee since 1982 and was instrumental in developing the JEDEC outlines for BGA, PGA and TAB packages. Mr. Hayward can be reached at james. hayward@amd.com or by phone at 408.982.6427.