Gigascale Integration Will Transcend Current Interconnection Limits

A new Interconnect Focus Center research program for gigascale integration (GSI) has been established to discover and invent new solutions enabling the U.S. semiconductor industry to transcend known limits on interconnections.

Left unchanged, these GSI interconnect limits would otherwise slow or halt the historical rate of progress of gigascale integration.

This 39-month, $19.5 million IFC program is jointly funded by the Defense Advanced Research Project Agency (DARPA) and the Microelec-tonics Advanced Research Corp. (MARCO), which is funded by the Semiconductor Industry Association, San Jose.

Georgia Tech is the prime contractor and lead institution in the multi-university research consortium, which also includes Cornell, MIT, Rensselaer, Stanford and SUNY-Albany. Prof. James D. Meindl, director of the Georgia Tech Microelectronics Research Center is IFC director.

Virtually all contemporary architectures for microprocessor and logic chips are derived from currently obsolescent, original implementations whose performance and cost were dominated by transistor properties, as opposed to interconnect properties.

Consequently, a key forward looking feature of the IFC program will be a research effort dealing with interconnect-centric micro-architectures. Core tasks will deal with materials and processing, process modeling and simulation and reliability and characterization.

Early 21st century opportunities for gigascale and terascale integration will be governed by a hierarchy of physical limits with five levels. These are:

1. The fundamental limits imposed solely by the basic laws of physics
2. Material limits resulting from the properties of particular conductor, semiconductor and insulator materials
3. Device limits arising from the characteristics of specific device structures
4. Circuit limits pertinent to distinctive circuit configurations
5. System limits which specify boundaries that a system-on-a-chip must not trespass.

1. System Architecture, including new frontier explorations of novel instruction set architectures as well as novel 2-D and 3-D micro-architectures that make communication more visible to the programmer and the compiler
2. Physical Design Tools, including the creation of a new frontier library of 3-D "interconnect cells"-akin to familiar libraries of standard logic cells
3. Novel Communications Mechanisms including the use of new-frontier, on-chip hetero-epitaxial photon sources, optoelectronic polysilicon waveguides and polycrystalline SiGe modulators/detectors for photonic clock distribution and data communication as well as microwave RF techniques
4. Chip-to-Module Interconnects based upon new frontier explorations of novel wafer-level batch-packaging (WLBP) technology that extends normal back-end-of-the-line batch processes to include additional "tail-end-of-the-line" batch processes to produce fully packaged "dice" that are then fully tested electrically for both function and performance prior to wafer separation
5. Materials and Processing including new frontier explorations of advanced active three-dimensional (3-D) interconnect concepts, organic engineered materials for electronic and optical structures as well as novel models for the effects of surface and grain boundary scattering on resistivity of sub-100 nm thin films
6. Process Modeling, Simulation, and Technology Assessment including development of new frontier process models for spatial variations of interconnect parameters & 3-D predictive models-for atomic arrangements, point defects and grain boundaries-that enable simulation of properties for performance, reliability and manufacturability
7. Reliability and Characterization, including new frontier explorations of markedly improved novel physical models for electromigration that account for the impact of nucleation spot density on the formation of voids in metal interconnect patterns; novel material characterization techniques using microspectroscopy