July - August 1999
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Lead-on-Chip Package Extends the Use of
Wire Bonding and Leadframe Technology
By David Francis and Linda Jardine
International Interconnection Intelligence, Montara, Calif.
L.G. Semicon Co., Ltd.
Bottom Lead Semiconductor Package Having Folded Leads
There is still a very large infrastructure of wire bonders and leadframe manufacturing, and it has been the goal of many companies to extend the use of this technology as much as possible.
Figure 1 illustrates a lead-on-chip (LOC)-type package that extends the use of wire bonding and lead-frame technology while at the same time shrinking the package size.
Figure 1. Previous LOC process
While this approach appears very viable, there are three reasons why an improved design is necessary. For those of you who like a challenge, identify the three drawbacks to this package design given by L.G. Semicon. One should be very obvious, the second one less so, and the third one is really extra credit. The three reasons are given at the end of this article.
Figure 2 illustrates the basic improved package design. The ends of the leads are folded over in a very tight bend to form what amounts to a doubly thick leadframe.
Both parts of the leadframe are molded. The only exposed portion is the bottom surface of the bottom lead. This surface is plated with lead or tin to prevent corrosion to it and facilitate solder wetting. The leads are trimmed near the edge of the package.
An optional shallow groove is formed in the bottom surface of the outer lead if additional bending is to be done.
The wire bond surface of the lead is plated with silver or gold to facilitate bonding and to improve electrical performance.
A variety of lead configurations, not available with the previous design, are now available. The leads can be formed to offer improved standoff height, increased compliance and inspectability of the solder joints.
The higher the standoff height, the easier it is for air to flow under the package and assist in the heat removal process.
Another possible advantage of forming the leads so they slope or point down is that the leads have a greater tendency to penetrate the solder on the PWB pads.
If the package is sufficiently light, the package with the horizontal leads will tend to sit on the surface of the solder. This could result in opens if the solder level is not coplanar.
Assuming the leads are coplanar when bent at an angle, the solder should form an easily inspectable fillet at each lead.
- Easy. There is very little compliance between the package and the substrate. Thermal cycling causes cracking of the solder connections.
- Moderate. Can't inspect the pad connections. The package pads do not appear to be supplied with a large volume of solder (e.g., a solder ball). The solder layer is most likely applied by plating or screen printing. Any variation in coplanarity or solder volume on the substrate pads is likely to result in an open. Since the pads are hidden by the package, it is not possible to visually inspect for opens.
- Difficult. Heat emission from the package is poor. It would appear that, because the package is so close to the surface of the PWB, there is little or no air movement under the package and that what heat is coupled down into the PWB via the leads is not adequate for the application.
Figure 2. Improved lead frame configuration (basic)
International Interconnection Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection areas. Contact David Francis or Linda Jardine by e-mail at firstname.lastname@example.org or by phone at 650.728.5270.