Hyundai Lead-on-Chip CSP Fabricated with Several Layers of Flexible Circuits
|David Francis and Linda Jardine
Hyundai Electronics Industries Co., Ltd.
"Chip-Size Semiconductor Package Fabrication Method Thereof"
This patent describes a lead-on-chip (LOC) type CSP that offers improved solder-joint reliability and thermal performance over the previous generation package. The complete process is not well specified, which may indicate the preliminary nature of this concept.
The manufacturing process described could easily be accomplished on a high-speed flex or TAB line. It may be possible to provide the first layer circuitry and interconnect at the wafer level.
Two examples of prior art are provided. The first is a standard TSOP package, offered as an example of a package with an excellent history of forming reliable solder joints.
The second example is a bottom-leaded package (BLP) with a design also patented by Hyundai. It seems that the prior BLP design did not have the same high solder joint reliability as TSOPs. The BLP joints have shown a higher incidence of delamination and cracking.
Another limitation to these two earlier packages is that the ICs are surrounded by mold resin, which limits the removal of heat from the devices.
In this patent, a rather simple method is used to form the package leads. In its basic configuration, the package is fabricated using what appears to be several layers of flexible circuitry.
In the wire-bonded version, a flex layer is adhesively bonded to the face of the chip. The chip contains the bond pads in its center, and wire bonds are used to connect the chip pads to the leads on the first flex layer.
The first layer consists of an adhesive layer, an insulation layer and a conductive layer. No further information is provided. This approach can also be used with a bumped die, but no specifics were provided. A second flex layer is then attached to the first layer as shown in the illustration. The only construction detail provided indicates that the two sets of leads (flex circuits) are formed in a similar manner.
The two layers are bonded together to complete the interconnect process. A coating of high-temperature solder can be applied to the second flex layer and used for bonding the two flex circuits together.
The bonded device is then encapsulated as shown. No encapsulation method is specified, but molding would provide the best surface for the next step of the process, where adhesive is applied to the top surface of the encapsulation where the leads are to be terminated.
The leads on the second flex are then bent up to form a shape similar to the J-shaped leads found on PLCC and SOJ packages. The adhesively bonded lead ends limit the range of lead movement.
This lead-on-chip package utilizes multiple layers of flex circuits.
The design described in this patent appears to solve the two problems identified in the prior art, poor thermal performance and solder joint reliability. In this package, the chip is exposed for improved thermal transfer. However, attaching a heat sink to the chip with the flex leads may be a challenge.
The lead design should be improved over the previous BLP leadframe approach. The leads are flexible, and the shape should enable the formation of adequate solder fillets on both sides of the J bend. If the leads are left as part of a strip, rather than being singulated, the polyimide layer between leads could keep them aligned and provide additional support.
International Interconnection Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection areas. Contact David Francis or Linda Jardine by e-mail at email@example.com or by phone at 650.728.5270. [iii1.com]