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Current Issue
An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics
August - September 2001

Bond Integrity: Trade-Offs Between Electrical, Thermal and Mechanical Performance

ABSTRACT
Bond integrity has broad connotations in today's semiconductor industry. IC assembly requires probing, gluing, sputtering, joining, encapsulating, globing, molding, interconnecting, underfilling and attaching or welding together package and board assemblies. All of these operations involve bonding, and the integrity of these bonds is vital.

Computer modeling is used to analyze stresses and improve bond integrity.

Dr. Timothy W. Ellis, Kulicke and Soffa Industries, Willow Grove, Pa.

In this day of 1.5 Ghz desktop computers, PDAs, cellular communications, HDTV and the Internet, such seeming minutiae as bonding the "Silicon Miracle" to the outside world might seem of little technological interest or concern. In fact, the opposite is true.

Because of the exponential expansion of silicon-driven technology, bonding for enhanced semiconductor performance continues to pose dynamic challenges in R&D to support the continued sophistication of the IC.

Moore's Law of Circuit Density and Performance states, in part, that the number of transistors on a device doubles every 18-24 months. This provides the backdrop for ever-increasing I/O counts and the resulting decrease in interconnection pitches.

For assembly to keep pace, bonding must also address a myriad of other issues that are a direct result of Moore's Law.

Higher Stresses

Higher numbers of transistors/device unit area directly result in the need for higher thermal load dissipation into ambient air. The higher stresses found in many new packages are a direct result of larger thermal gradients or package processing requirements (e.g., no-lead soldering operations).

In addition, smaller package footprints reduce the area of joints, typically by the square of the package size reduction, resulting in less total mechanical tenacity.

Environmental/reliability difficulties may result from the previously mentioned thermal and mechanical issues. In addition, higher temperatures may lead to increased chemical activity, and higher mechanical stress can cause more rapid propagation of cracks and voids that may combine to cause failure.

Figure 1. Mechanical fatigue testing of gold wire is a traditional stress test.

Mechanical Integrity

Verification of mechanical integrity is often the first line of defense in semiconductor assembly. Wirebond, flip-chip and die-attach shear tests are common screening criteria that are online in assembly houses. (Figure 1 illustrates a traditional method of mechanical fatigue testing.)

Thermal cycling tests push the limits of cyclical fatigue behavior beyond that found in actual use. These tests, however, do not necessarily verify total mechanical bond integrity.

The elements of mechanical bond failure were first explored by Griffith(1). In his theory, a balance is struck between the mechanical stress applied and the creation of new surface area, which has an associated, integrated surface energy. Surfaces may adhere by one or several mechanisms acting in concert.

True metal/metal chemical bonds are formed in wirebond or solder ball reflow when metals dissolve into each other, forming alloys and intermetallic compounds. Surface roughness can allow one surface to entrain another material within its pore structure, such as polymer adhesion to a porous ceramic substrate.

Other attractions are also possible. Van der Waals bonding can be present, essentially taking advantage of the attraction between two masses(2).

Hydrogen bonding may also be involved. The difficulty of removing absorbed water in semiconductor packaging operations attests to the strength of these bonds.

Mechanical integrity is therefore intimately linked with chemical integrity. Mechanical bonds are formed by cohesive, tenacious and uniform chemical processes. Even the lowly fastener owes its usefulness to the diffusion bonding of the nut to the bolt shank to prevent self-disassembly due to the mechanical forces of tensioning.

In modern semi-conductor packages, mechanical integrity is the keystone for all other problems, including electrical and thermal anomalies.

At the same time, management of the physical bonding process and assuring its integrity has become more difficult.

Figure 2A. Computer modeling of stresses in the ball and underlying pad during wire bonding Figure 2B. Stresses in the bond pad structure caused by thermal cycling of a flip-chip package Figure 2C. Stresses caused by thermal cycling of a substrate

CTE Mismatches

Stress on a package may result from several sources (Figures 2A-2C). Coefficient of thermal expansion mismatches is one example. In the multiple reflow cycles often used in package and board assembly, polymer materials (CTE = 17 ppm-25 ppm) must remain firmly adhered to silicon (CTE = 4 ppm).

Substrates and die themselves may have residual stress stored within their structure. Residual stress can change the distribution of forces within the package from what was intended in the original design, causing unexpected delamination or cracking failures.

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