The Influence of CSPs on Evolutionary Product Designs

By Dale E. Lee, Iomega Corp., Roy, Utah

Component packaging was once the sole domain of the IC fabricator and/or IC package supplier, with a "what you see is what you get" mentality for the package consumer.

This attitude placed strains on PC board designers, fabricators, automated assembly equipment suppliers and board assemblers on the implementation of these packages into their designs and assembly processes.

Over the years, relatively few changes have occurred in this system of new component packaging development and production. Now, with the advent of the ball grid array and chip-scale package, the rules of component packaging technology are being rewritten. These component packages provide the increased circuit densities needed for today's product designs. Many of these components utilize single and multi-layer substrate materials as the basis for the package.

Vertical Integration

Using these package types, it is possible to integrate portions of the PCBA-level design into the component package design for custom and even some off-the-shelf components. This level of vertical integration between IC interconnection, PC board and PCBA design, when implemented early in the product design life cycle, may yield a lower cost/higher performance product solution than optimization of the individual elements.

This potential integration requires a change in the normal level of concurrent engineering support required during the development of a new product. The silicon die fabricator and/or IC package assembly house should be represented as part of the product development design team.

This paper will address the development of a CSP disk drive controller ASIC at Iomega for use in a removable media drive.

Via Pad, Line/Space Conditions	Number of Signal/Plane Planes	1 or 2-sided Attachment	Controller Comonent Package	Wiring Compacity Available	Routing Resources Used(%)	Notes
25/5/5	4S	128 QFP	234	84	17.85	PCA to Think
25/5/5	2S/2P	128 QFP	200	104	20.88	PCA to Think
25/6/6	2S/2P	128 QFP	195	104	21.95	PCA to Think
25/5/5	2S/2P	128 QFP	149	104	28.04	QFP's in Cavity
25/5/5	2S/2P	128 QFP	257	103	16.25	QFP's in Cavity
25/5/5	4S	99 QFP	293	91	12.46	CSP Req. 3 Layers
25/5/5	2S/2P	99 QFP	147	91	24.92	CSP Req. 4 Layers
10/4/4	4S	99 QFP	227	108	19.01	Microvia/Short PCB
10/4/4	2S/2P	99 QFP	182	108	23.68	Microvia/Short PCB
Design with routing resources used (Percentages greater than 23% used are very defficult to route)

Conceptual Design

Early in the product development life cycle, the issues relating to component packaging, PC boards and assembly were identified and evaluated for potential impacts to the program. (Table 1. provides a partial list of development issues addressed during conceptual design.)

As a result of the development issues' analysis, we determined that the program required the development of four silicon devices. Three of the devices would be evolutionary designs and one would be a new design.

We determined that the drive controller ASIC package was the critical element due to the large space allocation it required for the standard leaded SMT package. An additional problem with the controller ASIC was the need for backward compatibility with its predecessor. Therefore, this component needed to be assembled in multiple packages depending on the functional application and end-product design.

Cost Reductions

Future cost reductions, due to process technology migration, would be performed on all ASIC designs where feasible. The form factor of the end-product design would be a critical parameter with multiple restrictions on component packaging and PC board design.

The PC board was to be limited to four layers, and component package heights were to be restricted to less than 1.2 mm in critical areas.

Testing

Testing of the controller ASIC would be accomplished on a Trillium IC logic test system, with a 92 percent minimum deterministic fault grade requirement. Test of the final assembly would consist of in-circuit test for manufacturing defects and functional test for electrical defects.

PC Board/PCBA Predictive Design Analysis

Early in the development of the project, a functional block diagram, preliminary bill of materials, component packaging analysis, PCBA space allocation analysis and interconnect density analysis were performed to determine the component packaging, PC board interconnection and PCBA requirements.

The PCBA space allocation analysis consisted of placing mechanical outline shapes for each of the component packages and corresponding component mounting land patterns on the preliminary function block and PCBA interconnection layout (Figure 1).

Figure 1. Preliminary function block and PCBA interconnection layout

This analysis was performed to determine the component packaging and PC board interconnection requirements. The controller ASIC's package was simulated using a standard 160-pin QFP, 121-pin BGA and a "similar to" CSP component. It became apparent that the available space for the electronics would be severely limited by the controller ASIC's package(due to pin count)dominating the layout of the PC board and the functional inter-connectivity of the final assembly.

The interconnect density analysis consisted of performing a total wiring demand for the proposed assembly to verify that the product design would be routable within the mechanical packaging constraints.

A "total wiring demand" analysis, shown below, was performed to provide an indication of the number of layers needed to route the PC board within predetermined form factor requirements. The analysis indicated that the design might be routable in four layers. PCA Wiring Demand Analysis:

>Comp.PCB Wire Demand = PCB Wire Capability
					  Wd  =  Wc
					  
Formula:
(*  Sqrt[(parts/sq.in.)]*(ave. leads/part) = 
layout efficiency*(tracks/channel)*(signal layers)/
(channel width)

Results:
Wd = 76 to 89
Wc = 72 ( 3 layers & 3 tracks/channel) or
   = 96 ( 4 layers & 3 tracks/channel)

The proposed design can be placed and routed within the existing constraints. An additional analysis was performed using the SavanSys software package from Savantage. The software integrates the PC board design, component packaging, fabrication cost and assembly cost information into a predictive software system.

The results of the SavanSys software analysis (shown in Table 1), combined with the previous "total wiring demand" analysis results, indicated that the controller ASIC would have to be placed into a high density interconnect package.

Due to the removable media disk drive under development, and a 1.2 mm height restriction on all components, the SavanSys analysis determined that all standard IC packaging would not meet the Z-axis and component package area form-factor requirements. These packages included 0.4 mm pitch, leaded plastic quad flat pack (QFP), thin quad flat pack (TQFP) and ball grid array (BGA).

Furthermore, recessing these components into cavities to meet Z-axis requirements would not provide enough area to route the printed circuit board.

Concerns were identified related to the escape routing for the CSP components within the number of layers allowed in the product design. SavanSys determined that the CSP could be escape routed in three to four layers using standard through-hole via techniques. The use of microvias would meet all form factor requirements and allow for shrinkage of the PC board.

Alternatives

Die and near-die-level packaging was evaluated as an alternative to standard packaging. Chip-on-board (COB) and flip-chip packaging were also considered and rejected. COB wirebond fan out requirements provided minimal reduction in area over standard packaging and was therefore eliminated. Flip-chip packaging was eliminated due to the immaturity of the ASIC design, potential limitation of known good die(KGD)and availability of qualified subcontract assemblers to meet projected production schedules and volumes.

Tessera's µBGA format was the CSP that best met the profile height, PC board footprint and pin-count requirements.

An estimated die size was derived from "similar to" ASIC designs. Based on the die size, a maximum number of available balls was estimated for various pitches up to a maximum of 99 balls in a full array.

Iomega estimated that the die would require from 105 to 108 signals in the desired application. Upon further analysis of the component packaging, we determined that by combining some ground lines in the substrate layer, the die could be assembled in a 99 ball chip-scale package. However, due to the full array design and the pitch of the balls, no future cost reductions due to die shrinkage would be possible.

The Impact on Device Design/Layout

The scope of the program required that the chip under design fit into the footprint and pinout of another existing disk controller chip, for manufacturing flexibility. There were four other drive platforms that would use the same chip, all in different packages.

It was necessary to devise a layout that would fit into a chip- scale package measuring 14 X 14 mm, a 100-pin PQFP package, a 14 X 20 mm 128-pin PQFP package,a 28 X 28 mm 160-pin PQFP package and a 15 X 15 mm 121-ball BGA package with the 100-pin PQFP pinout already defined by the existing controller chip.

Package Design

The chip-scale package could be designed as a fan-in only design, or as a fan-in/fan-out design. The advantage of the fan-in/fan-out design was the larger ball pitch at 1.0 mm, which was more easily manufactured. The downside to the fan-in/fan-out design was increased real estate consumption on the board and higher cost. For this reason, a fan-in only design was selected.

The package design was ultimately defined as a 9 X 11 array, 0.5 mm ball pitch, fan-in only, 99 ball, 7 mm by 6 mm footprint, with a profile height under 0.9 mm. Several design iterations were required to fully design the package.

The 99 ball chip-scale package presented a constraint on the layout of the ASIC, since the 99 balls were in a 9 by 11 array, and this array necessitated a rectangular die size.

Another constraint was presented by the CSP, as the manufacture of the package required a minimum pad pitch of 4.25 mils, which was considerably above the minimum pad pitch of the IC fabrication process.

Other layout constraints included placing no pads in the corners of the die, leaving space for tape tie bar connections, and limiting the number of pads that could be placed on each side of the chip.

The various packaging constraints had a significant impact upon the layout of the device, and many pad layouts were evaluated, with each of them failing in some aspect. A good layout for the CSP would cause bond wires to short together in the 128-ball PQFP package.

Moving pads around to make the 128-ball PQFP work was difficult because of the need to fit the existing 100-ball PQFP footprint. It then became necessary to devise a new 99-ball CSP routing scheme. Sure enough, this would then break another package's requirements.

The largest constraint the program faced was the necessity to fit into the already established footprint of the existing controller device. There was very little leeway in moving the locations of 100 of the 160 pads.

The "simple" act of swapping the locations of two adjacent pads required a wiring analysis across five package types. The team explored using a ground ring on the periphery of the CSP to simplify both ground routing from the chip to the package and PC board routing. Several designs were evaluated that solved both chip layout difficulties and PC board routing hardships too, however, there was a risk associated with the ground ring as it had never been attempted before. For that reason, the ground ring was abandoned.

Engineering Concerns

Product engineering concerns forced the team to move some of the power and ground pad locations for current balancing, and our layouts broke again because of this requirement. After more iterations, a pad layout/CSP route was finally devised that met all the requirements. (Some of the 99-ball CSP layout options are shown in Figure 2.)

New Engineering Approach Required

The interactive process of devising a pad layout/CSP route required much communication and collaboration between the engineering teams at both companies. Once the "magic" combination of a chip-pad layout and a CSP routing scheme had been found, the next step was to determine if it was realistic from a product engineering prospective.

Questions like, "Are there enough power and grounds?" "What will the inductance of the chip-scale traces be?" and "How can we model the device in a CSP to answer these questions?" came up.

Much more work was ahead of us. The inductive characteristics of the PQFP and TQFP packages were well known, and the BGA package posed no real mysteries in this area either. However the CSP was an unknown.

First, it was necessary to model the inductance of the CSP. The capacitance of the traces was clearly negligible, as was the resistance. Second, it was necessary to determine the current carrying capacity of the traces.

Current capacity was determined experimentally using what is basically the brute force approach. Various currents were forced onto a trace on a sample package until the trace burned up. We determined that a 38-micron wide single trace on a package would conduct 1.3 amperes of current, before the mysterious encapsulated smoke that seems to make electronics work escaped from the trace, and the magnitude of the current required to burn up a trace surprised all of the team.

Since 1.3 Amperes is more than enough current to burn up a wire bond to the silicon die, we concluded the current carrying capacity of the CSP's traces was quite adequate.

Inductance Modeling

The next challenge was to model the inductance of the traces on the CSP for power and ground modeling concerns. The device under design was required to support a modest 40 MHz clock rate, which is a low maximum operating frequency for the IC fabrication process employed.

After some study it became obvious the power and ground traces on the CSP were in fact going to be tied together at the board level, which put them all in parallel, even though they were separated on the chip. In fact, the chip was to have five separate power busses and five separate ground busses, to assist in Iddq testing.

All of the grounds were tied together in the routing of the CSP as well, to a common set of two connected ground balls in the center of the 99-ball array. A 2D finite element analysis was run on a trace cross section. The cross section dimensions were:

	Width = 38 microns
	Height = 18 microns
	Per Unit Inductance = 0.81 nH/mm 
    (Ansoft 2D Model)

To calculate actual trace inductance, the ball pitch (0.5 mm) was used as a yardstick to measure the distance to the outer row of balls. Then a value of 0.725 mm was used as the distance from the outer ball row to the bonding pads on the die. The calculation yielded:

The tolerances should be on the order of ±0.125 mm or ±0.1 nH, since the trace lengths were approximations. Since there were six ground traces running from the die to the common ground ball, the total inductance became:

_______________1______________
(1/L + 1/L + 1/L + 1/L + 1/L + 1/L)

Which yielded a final value of 0.483 nH (using a worst case calculated trace inductance value of 2.9 nH/trace). Using this value, SPICE simulations were run to determine the potential for ground bouncing. Once again, the CSP proved to be surprisingly robust. High-current-carrying capacity on very short traces with low inductance and capacitance makes for a very good IC packaging technology.

Figure 2. Interposer design options

Conclusion

The successful completion of this project required much communication and collaboration between not only the two companies, Iomega and the software vendor, but also between many departments within Symbios Logic and Iomega. The product engineering, test engineering, applications engineering physical design, logic design, package development and strategic account management groups all worked with Iomega engineering groups on the project. This level of concurrent engineering was new to both companies and also proved to be very educational. The exchange of information and expertise was gratifying, and served as a model for future development programs. The lessons we learned were many, and the following table summarizes what we discovered about CSPs:

• The miniaturization requirements of mechanical systems drive the need for CSPs.
• With sufficient forethought, CSPs can simplify PC board and system design.
• CSPs, in turn, drive the design and layout of the chips themselves.
• Silicon vendors must be aware of the impact of CSPs to be successful, and should be especially knowledgeable about the test ramifications.

Acknowledgments

The author acknowledges the following individuals for their assistance: Jeff Johns and Ron Steel of Symbios Logic and Leonard Sherman of Iomega Corp.

Mr. Lee has been involved in surface mount design, package & process development and production for eighteen years in various technical and managerial positions for multiple corporations (Texas Instruments, Motorola, Unisys, Evans & Sutherland). In his current position as Staff Engineer at Iomega Corporation, he is responsible for research, development and implementation of advanced manufacturing , component packaging and interconnect techniques for high volume production applications. These activities include design and development of CSP & BGA packages, PCB & PCBA subcontractor support, flex & rigid PCB/PCBA DFM analysis, process development, product qualification and new product introduction.

Mr. Lee has degrees in Chemistry and Chemical Engineering and has published several papers on SMT design, assembly and rework.

Dale Lee, Iomega Corporation, 1821 West Iomega Way, Roy, UT 84067. Tel: 801-778-3768, fax: 801-778-3495, email: leed@iomega.com

References

1. G. Coors, G, Anderson, et al., "A Statistical Approach to Wiring Requirements," Proceedings of the IEPS, 1990, pages 774-783.
2. H. Holden, "Design And Fabrication Issues in the Use of Flip Chip and High-Density Area Array Packages," Proceedings of the Emerging Technologies Symposium, 1997, pages 91-98.