September 1998 - ChipScale Review

September 1998


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Definable Package Features a Must for Standardization


By James L. Hayward
Contributing Editor

The process of standardization begins, naturally enough, with identification of the common features of the objects being standardized.

With IC packages, these features may possess constant values for all members of the family, or may be definable by algorithmic progressions. Ball pitch for BGAs would be an example of a constant-valued feature, and body size would be an example of a feature which could be described by a defined progression of values. Even before this segregation of features can be made, however, we must define classes of objects with definable features. For example, in the broad category of IC packages, we must separate QFPs from BGAs before any meaningful standards can be defined for either package type.

Chip-scale packages (CSPs) are the package type receiving the most interest in standards organizations today. A commonly quoted definition of a CSP is a package where the body size is <1.2X the size of the die being packaged. From a standards point-of-view, this definition is not very useful, since many different package configurations, both current and historical, are included within it.



Figure 1. The major CSP outlines can be devided into
leadframe-based packages ad BGA-type packages


And, as with the QFP versus BGA in the example cited above, different configurations of CSPs will require different approaches to standards definition. The standards groups must distinguish fundamental differences in outline, differences resulting from material construction and, in some cases, differences in function.

CSP outlines can be differentiated into two groups as shown\:

  • Leadframe-based packages: variants of SO or QFP packages commonly known as SON or QFN where N indicates "no lead";
  • BGA-type packages: variants of BGA packages with pitches <1.0 mm commonly known as FBGA where F indicates "fine pitch".
The second category, BGA-type packages, can further be split into two subgroups:

  • FBGAs with fixed body sizes independent of die size (the package substrate extends beyond the die edge in one or both directions);
  • FBGAs with body sizes which are closely coupled to the die size and will change size as the die changes size.
To borrow from EIAJ coinage, type 2a is a "flange-type" FBGA, since the substrate can be described as a flange extending out from the die, and type 2b is a "real chip-size" FBGA.

The JEDEC JC-11 Committee pursues active efforts to define outline requirements for all three types of CSPs and to accommodate the special problems of each type. Outlines for the Type 1 SON packages have been defined in the registrations MO-196 and MO-197 in JEP-95 and also in a design guide in Section 16 of JESD 95-1.

Type 2a FBGAs are represented by the registrations MO-195 and MO-205 in JEP-95 and there is a design guide section of JESD 95-1 in process. There is also current action within JEDEC to define outlines and a design guide for the type 2b FBGAs.

Mr. Hayward is a Senior Member of Technical Staff in the Manufacturing Services Group at Advanced Micro Devices (AMD), Sunnyvale, Calif. He has been the AMD member of the JEDEC JC-11 Committee since 1982 and was instrumental in developing the JEDEC outlines for BGA, PGA and TAB packages. Mr. Hayward can be reached at james.hayward@amd.com or by phone at 408.982.6427.

The major CSP outlines can be divided into leadframe-based packages and BGA-type packages.

"CSPs are the package type receiving the most interest in standards organizations today."



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Standards, 98/10/01, 05/13/99, ID=9809/j.hayward1
Keywords=af00

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